Related papers: Generalizable Verilog Modeling Framework for Synch…

It has been suggested that Rapid Single Flux Quantum (RSFQ) devices could be used as the classical interface of superconducting qubit systems. One problem is that the interface acts as a dissipative environment for a qubit. Recently ways to…

Accurate and low-latency qubit state measurement is critical for trapped-ion quantum computing. While deep neural networks (DNNs) have been integrated to enhance detection fidelity, their latency performance on specific hardware platforms…

While witnessing the noisy intermediate-scale quantum (NISQ) era and beyond, quantum federated learning (QFL) has recently become an emerging field of study. In QFL, each quantum computer or device locally trains its quantum neural network…

An essential part of cyber-physical systems is the online evaluation of real-time data streams. Especially in systems that are intrinsically safety-critical, a dedicated monitoring component inspecting data streams to detect problems at…

Large-scale timers are ubiquitous in network processing, including flow table entry expiration control in software defined network (SDN) switches, MAC address aging in Ethernet bridges, and retransmission timeout management in TCP/IP…

In the model of gate-based quantum computation, the qubits are controlled by a sequence of quantum gates. In superconducting qubit systems, these gates can be implemented by voltage pulses. The success of implementing a particular gate can…

Artificial neural networks inspired by brain operations can improve the possibilities of solving complex problems more efficiently. Today's computing hardware, on the other hand, is mainly based on von Neumann architecture and CMOS…

Single-Flux Quantum (SFQ) digital logic is typically energy efficient and fast, and logic that uses ballistic and reversible principles provides a new platform to improve efficiency. We are studying long Josephson junctions (long JJs), SFQs…

This work presents a hardware and software architecture which can be used in those systems that implement practical Quantum Key Distribution (QKD) and Quantum Random Number Generation (QRNG) schemes. This architecture fully exploits the…

Field-Programmable Gate Arrays (FPGAs) are widely used in modern hardware design, yet writing Hardware Description Language (HDL) code for FPGA implementation remains a complex and time-consuming task. Large Language Models (LLMs) have…

Synaptic delay parameterization of neural network models have remained largely unexplored but recent literature has been showing promising results, suggesting the delay parameterized models are simpler, smaller, sparser, and thus more…

Large language models (LLMs) have demonstrated remarkable performance across a wide range of natural language processing tasks. However, their exponentially increasing parameters pose significant challenges for deployment on…

As large language models (LLMs) grow in size and deployment scale, quantization has become an essential technique for reducing memory footprint and improving inference efficiency. However, existing quantization toolkits often lack…

Meeting service-level objectives (SLOs) in Large Language Models (LLMs) serving is critical, but managing the high variability in load presents a significant challenge. Recent advancements in FP8 inference, backed by native hardware…

We present a continuous-time, neural-network-based approach to optimal control in quantum systems, with a focus on pulse engineering for quantum gates. Leveraging the framework of neural ordinary differential equations, we construct control…

Reducing space and time overheads of fault-tolerant quantum computation (FTQC) has been receiving increasing attention as it is crucial for the development of quantum computers and also plays a fundamental role in understanding the…

As the complexity of logic designs increase, new avenues for testing digital hardware becomes necessary. Fuzz Testing (fuzzing) has recently received attention as a potential candidate for input vector generation on hardware designs. Using…

The advancement of functional safety has made RTL-level fault simulation increasingly important to achieve iterative efficiency in the early stages of design and to ensure compliance with functional safety standards. In this paper, we…

In the current NISQ era, there is demand for functional quantum devices to solve relevant computational problems, which motivates a utilitarian perspective on device design: The goal is to create a device that is able to run a given…

Portability of hardware designs between Programmable Logic Devices (PLD) can be accomplished through the use of device-agnostic hardware description languages (HDL) such as Verilog or VHDL. Hardware designers can use HDLs to migrate…