Efficient Synaptic Delay Implementation in Digital Event-Driven AI Accelerators
Abstract
Synaptic delay parameterization of neural network models have remained largely unexplored but recent literature has been showing promising results, suggesting the delay parameterized models are simpler, smaller, sparser, and thus more energy efficient than similar performing (e.g. task accuracy) non-delay parameterized ones. We introduce Shared Circular Delay Queue (SCDQ), a novel hardware structure for supporting synaptic delays on digital neuromorphic accelerators. Our analysis and hardware results show that it scales better in terms of memory, than current commonly used approaches, and is more amortizable to algorithm-hardware co-optimizations, where in fact, memory scaling is modulated by model sparsity and not merely network size. Next to memory we also report performance on latency area and energy per inference.
Cite
@article{arxiv.2501.13610,
title = {Efficient Synaptic Delay Implementation in Digital Event-Driven AI Accelerators},
author = {Roy Meijer and Paul Detterer and Amirreza Yousefzadeh and Alberto Patino-Saucedo and Guanghzi Tang and Kanishkan Vadivel and Yinfu Xu and Manil-Dev Gomony and Federico Corradi and Bernabe Linares-Barranco and Manolis Sifalakis},
journal= {arXiv preprint arXiv:2501.13610},
year = {2025}
}
Comments
arXiv admin note: substantial text overlap with arXiv:2404.10597