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Using Optical Orthogonal Frequency Multiplexing (O-OFDM), variable bandwidth channels can be created in Elastic Optical Networks (EON). This allows the use of spectrum more efficiently by allocating integral multiple of basic bandwidth…

To achieve multi-Gb/s data rates in 6G optical wireless access networks based on narrow infrared (IR) laser beams, a high-speed receiver with two key specifications is needed: a sufficiently large aperture to collect the required optical…

Wrinkles and nanobubbles are an integral and often unavoidable part of integrating 2D van der Waals semiconductors into actual device architectures. Despite their ubiquitous nature, quantitative correlation between such spatially…

Reconfigurable distributed antennas and reflecting surface (RDARS) has emerged as a promising architecture for communication and sensing performance enhancement. In particular, the new selection gain can be achieved by leveraging the…

Recent years have witnessed the growing deployment of optical circuit switches (OCS) in commercial GPU clusters (e.g., Google A3 GPU cluster) optimized for machine learning (ML) workloads. Such clusters adopt a three-tier leaf-spine-OCS…

The many cores design research community have shown high interest in optical crossbars on chip for more than a decade. Key properties of optical crossbars, namely a) contention-free data routing b) low-latency communication and c) potential…

Beyond-diagonal reconfigurable intelligent surfaces (BD-RISs) are an emerging RIS 2.0 technology for future wireless communication. However, BD-RISs are primarily passive without active amplification, suffering from severe multiplicative…

SoCs are now designed with their own AI accelerator segment to accommodate the ever-increasing demand of Deep Learning (DL) applications. With powerful MAC engines for matrix multiplications, these accelerators show high computing…

Oxidation of two-dimensional (2D) layered materials has proven advantageous in creating oxide/2D material heterostructures, opening the door for a new paradigm of low-power electronic devices. Gallium (II) sulfide ($\beta$-GaS), a hexagonal…

Emerging nano-scale programmable Resistive-RAM (RRAM) has been identified as a promising technology for implementing brain-inspired computing hardware. Several neural network architectures, that essentially involve computation of scalar…

Large language models (LLMs) exhibit memory-intensive behavior during decoding, making it a key bottleneck in LLM inference. To accelerate decoding execution, hybrid-bonding-based 3D-DRAM has been adopted in LLM accelerators. While this…

The great potential of memristive devices for real-world applications still relies on overcoming key technical challenges, including the need for a larger number of stable resistance states, faster switching speeds, lower SET/RESET…

Optimization of functionally graded metamaterial arrays with a high dimensional and continuous geometric design space is cumbersome and could be accelerated via machine learning tools. Mechanical metamaterials can manipulate acoustic or…

All-digital basestation (BS) architectures enable superior spectral efficiency compared to hybrid solutions in massive multi-user MIMO systems. However, supporting large bandwidths with all-digital architectures at mmWave frequencies is…

Sparse deep learning has reduced computation significantly, but its irregular non-zero data distribution complicates the data flow and hinders data reuse, increasing on-chip SRAM access and thus power consumption of the chip. This paper…

This paper presents a novel circuit (AID) to improve the accuracy of an energy-efficient in-memory multiplier using a standard 6T-SRAM. The state-of-the-art discharge-based in-SRAM multiplication accelerators suffer from a non-linear…

The rapid development of Artificial Intelligence (AI) and Internet of Things (IoT) increases the requirement for edge computing with low power and relatively high processing speed devices. The Computing-In-Memory(CIM) schemes based on…

DRAM scaling has exacerbated the RowHammer vulnerability. To counter this, JEDEC recently introduced Per Row Activation Counting (PRAC) with the Alert Back-Off protocol as an optional DDR5 feature. While promising, PRAC requires per-row…

Fully-analog in-memory computing (IMC) architectures that implement both matrix-vector multiplication and non-linear vector operations within the same memory array have shown promising performance benefits over conventional IMC systems due…

Topology optimization (TO) of 3D surface-enhanced Raman scattering (SERS) substrates faces challenges in managing field singularities and modeling orientation-averaged anisotropic molecules. We present 3D TO for manufacturable SERS…