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Large language model (LLM) decoding is a major inference bottleneck because its low arithmetic intensity makes performance highly sensitive to memory bandwidth. 3D-stacked near-memory processing (NMP) provides substantially higher local…

Hardware Architecture · Computer Science 2026-04-10 Chenyang Ai , Yixing Zhang , Haoran Wu , Yudong Pan , Lechuan Zhao , Wenhui OU

Modern Artificial Intelligence (AI) applications are increasingly utilizing multi-tenant deep neural networks (DNNs), which lead to a significant rise in computing complexity and the need for computing parallelism. ReRAM-based…

Emerging Technologies · Computer Science 2024-08-12 Bojing Li , Duo Zhong , Xiang Chen , Chenchen Liu

The Von Neumann bottleneck, which relates to the energy cost of moving data from memory to on-chip core and vice versa, is a serious challenge in state-of-the-art AI architectures, like Convolutional Neural Networks' (CNNs) accelerators.…

Hardware Architecture · Computer Science 2025-02-27 Cristian Sestito , Ahmed J. Abdelmaksoud , Shady Agwa , Themis Prodromakis

The substantial memory bandwidth and computational demands of large language models (LLMs) present critical challenges for efficient inference. To tackle this, the literature has explored heterogeneous systems that combine neural processing…

Hardware Architecture · Computer Science 2026-05-05 Yuzong Chen , Chao Fang , Xilai Dai , Yuheng Wu , Thierry Tambe , Marian Verhelst , Mohamed S. Abdelfattah

Processing in-memory (PIM) is promising to accelerate neural networks (NNs) because it minimizes data movement and provides large computational parallelism. Similar to machine learning accelerators, application mapping, which determines the…

Hardware Architecture · Computer Science 2024-07-02 Xuan Wang , Minxuan Zhou , Tajana Rosing

Compute-in-memory (PIM) mitigates the memory wall by performing computation within memory, reducing data movement and improving energy efficiency. DRAM-based PIM is particularly attractive due to its high density, mature manufacturing…

Hardware Architecture · Computer Science 2026-05-26 Siddhartha Raman Sundara Raman , Siyuan Ma , Lizy Kurian John

Deploying advanced large language models on edge devices, such as smartphones and robotics, is a growing trend that enhances user data privacy and network connectivity resilience while preserving intelligent capabilities. However, such a…

Hardware Architecture · Computer Science 2024-09-25 Zhongkai Yu , Shengwen Liang , Tianyun Ma , Yunke Cai , Ziyuan Nan , Di Huang , Xinkai Song , Yifan Hao , Jie Zhang , Tian Zhi , Yongwei Zhao , Zidong Du , Xing Hu , Qi Guo , Tianshi Chen

Neural networks (NNs) are growing in importance and complexity. A neural network's performance (and energy efficiency) can be bound either by computation or memory resources. The processing-in-memory (PIM) paradigm, where computation is…

Hardware Architecture · Computer Science 2023-03-28 Geraldo F. Oliveira , Juan Gómez-Luna , Saugata Ghose , Amirali Boroumand , Onur Mutlu

Processing-in-memory (PIM) has emerged as an enabler for the energy-efficient and high-performance acceleration of deep learning (DL) workloads. Resistive random-access memory (ReRAM) is one of the most promising technologies to implement…

Hardware Architecture · Computer Science 2024-03-29 Harsh Sharma , Gaurav Narang , Janardhan Rao Doppa , Umit Ogras , Partha Pratim Pande

The widespread adoption of Large Language Models (LLMs) has exponentially increased the demand for efficient serving systems. With growing requests and context lengths, key-value (KV)-related operations, including attention computation and…

Hardware Architecture · Computer Science 2026-02-13 Lian Liu , Shixin Zhao , Yutian Zhou , Yintao He , Mengdi Wang , Yinhe Han , Ying Wang

The first contribution of this paper is the development of extremely dense, energy-efficient mixed-signal vector-by-matrix-multiplication (VMM) circuits based on the existing 3D-NAND flash memory blocks, without any need for their…

Emerging Technologies · Computer Science 2019-08-08 Mohammad Bavandpour , Shubham Sahay , Mohammad Reza Mahmoodi , Dmitri B. Strukov

The Mixture-of-Experts (MoE) models have emerged as the state-of-the-art paradigm for scaling up large language models (LLMs) without proportionally increased computational cost. However, its on-device deployment faces a critical challenge…

Hardware Architecture · Computer Science 2026-05-25 Weikai Xu , Meng Li , Shuzhang Zhong , Tianyang Luo , Dongxue Zhao , Ling Liang , Zongwei Wang , Qianqian Huang , Yimao Cai , Ru Huang

The rapid advancement of Large Language Models (LLMs) has revolutionized various aspects of human life, yet their immense computational and energy demands pose significant challenges for efficient inference. The memory wall, the growing…

Hardware Architecture · Computer Science 2025-09-18 Hongyi Li , Songchen Ma , Huanyu Qu , Weihao Zhang , Jia Chen , Junfeng Lin , Fengbin Tu , Rong Zhao

Recently DRAM-based PIMs (processing-in-memories) with unmodified cell arrays have demonstrated impressive performance for accelerating AI applications. However, due to the very restrictive hardware constraints, PIM remains an accelerator…

Hardware Architecture · Computer Science 2023-10-17 Jaewoo Park , Sugil Lee , Jongeun Lee

3D Gaussian Splatting (3DGS) is an increasingly popular novel view synthesis approach due to its fast rendering time, and high-quality output. However, scaling 3DGS to large (or intricate) scenes is challenging due to its large memory…

Computer Vision and Pattern Recognition · Computer Science 2025-11-10 Hexu Zhao , Xiwen Min , Xiaoteng Liu , Moonjun Gong , Yiming Li , Ang Li , Saining Xie , Jinyang Li , Aurojit Panda

Processing-in-memory (PIM), as a novel computing paradigm, provides significant performance benefits from the aspect of effective data movement reduction. SRAM-based PIM has been demonstrated as one of the most promising candidates due to…

Hardware Architecture · Computer Science 2023-11-01 Cenlin Duan , Jianlei Yang , Xiaolin He , Yingjie Qi , Yikun Wang , Yiou Wang , Ziyan He , Bonan Yan , Xueyan Wang , Xiaotao Jia , Weitao Pan , Weisheng Zhao

In-memory database query processing frequently involves substantial data transfers between the CPU and memory, leading to inefficiencies due to Von Neumann bottleneck. Processing-in-Memory (PIM) architectures offer a viable solution to…

Recent nano-technological advances enable the Monolithic 3D (M3D) integration of multiple memory and logic layers in a single chip, allowing for fine-grained connections between layers and significantly alleviating main memory bottlenecks.…

The expansion of long-context Large Language Models (LLMs) creates significant memory system challenges. While Processing-in-Memory (PIM) is a promising accelerator, we identify that it suffers from critical inefficiencies when scaled to…

The deployment of large language models (LLMs) presents significant challenges due to their enormous memory footprints, low arithmetic intensity, and stringent latency requirements, particularly during the autoregressive decoding stage.…

Hardware Architecture · Computer Science 2025-11-03 Cenlin Duan , Jianlei Yang , Rubing Yang , Yikun Wang , Yiou Wang , Lingkun Long , Yingjie Qi , Xiaolin He , Ao Zhou , Xueyan Wang , Weisheng Zhao