Related papers: Row Hammer Effect and Floating Body Effect of Mono…

Over the years, the DRAM latency has not scaled proportionally with its density due to the cost-centric mindset of the DRAM industry. Prior work has shown that this shortcoming can be overcome by reducing the critical length of DRAM access…

We experimentally demonstrate a new widespread read disturbance phenomenon, ColumnDisturb, in real commodity DRAM chips. By repeatedly opening or keeping a DRAM row (aggressor row) open, we show that it is possible to disturb DRAM cells…

In order to shed more light on how RowHammer affects modern and future devices at the circuit-level, we first present an experimental characterization of RowHammer on 1580 DRAM chips (408x DDR3, 652x DDR4, and 520x LPDDR4) from 300 DRAM…

Memories that exploit three-dimensional (3D)-stacking technology, which integrate memory and logic dies in a single stack, are becoming popular. These memories, such as Hybrid Memory Cube (HMC), utilize a network-on-chip (NoC) design for…

This paper provides the fundamental mechanisms of two types of row activation-induced bit flips and proposes in-DRAM protection techniques. RowBleed occurs when a victim row experiences charge leakage due to transistor's threshold voltage…

The demand for accurate information about the internal structure and characteristics of dynamic random-access memory (DRAM) has been on the rise. Recent studies have explored the structure and characteristics of DRAM to improve processing…

Memory effects can have a profound impact on the resistivity of semiconductor systems, resulting in giant negative magnetoresistance and MIRO phenomena. This work opens the discussion of the memory effects in 3D conducting systems featured…

As Dynamic Random Access Memories (DRAM) scale, they are becoming increasingly susceptible to Row Hammer. By rapidly activating rows of DRAM cells (aggressor rows), attackers can exploit inter-cell interference through Row Hammer to flip…

Pr1-xCaxMnO3 (PCMO) based resistance random access memory (RRAM) is attractive in large scale memory and neuromorphic applications as it is non-filamentary, area scalable and has multiple resistance states along with excellent endurance and…

This paper challenges the existing victim-focused counter-based RowHammer detection mechanisms by experimentally demonstrating a novel multi-sided fault injection attack technique called Threshold Breaker. This mechanism can effectively…

DRAM read disturbance can break memory isolation, a fundamental property to ensure system robustness (i.e., reliability, security, safety). RowHammer and RowPress are two different DRAM read disturbance phenomena. RowHammer induces bitflips…

Processing-using-DRAM (PuD) is a promising paradigm for alleviating the data movement bottleneck using DRAM's massive internal parallelism and bandwidth to execute very wide operations. Performing a PuD operation involves activating…

1T1R (1-transistor-1-resistor) memory crossbar arrays represent a promising solution for compute-in-memory matrix-vector multiplication accelerators and embedded or storage-class memory. However, the size and scaling of these arrays are…

RowHammer stands out as a prominent example, potentially the pioneering one, showcasing how a failure mechanism at the circuit level can give rise to a significant and pervasive security vulnerability within systems. Prior research has…

RowHammer is a major read disturbance mechanism in DRAM where repeatedly accessing (hammering) a row of DRAM cells (DRAM row) induces bitflips in physically nearby DRAM rows (victim rows). To ensure robust DRAM operation, state-of-the-art…

Self-aligned single-dot memory devices and arrays were fabricated based on arsenic-assisted etching and oxidation effects. The resulting device has a floating gate of about 5-10 nm, presenting single-electron memory operation at room…

Li-ion battery performance is strongly influenced by their cathodes' properties and consequently by the 3D microstructure of the particles the cathodes are comprised of. During calendaring and cycling, cracks develop within cathode…

Three-dimensional (3D)-stacking technology, which enables the integration of DRAM and logic dies, offers high bandwidth and low energy consumption. This technology also empowers new memory designs for executing tasks not traditionally…

The semiconductor industry is reaching a fascinating confluence in several evolutionary trends that will likely lead to a number of revolutionary changes in the design, implementation, scaling, and the use of computer systems. However,…

The Last Level Cache (LLC) is the processor's critical bridge between on-chip and off-chip memory levels - optimized for high density, high bandwidth, and low operation energy. To date, high-density (HD) SRAM has been the conventional…