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Silicon-organic hybrid (SOH) platforms exhibit exceptional electro-optic (EO) properties, including high-speed operation, low energy consumption, and compact footprints. However, the absence of a scalable poling method for EO polymers,…
Modern DRAM is vulnerable to read disturbance (e.g., RowHammer and RowPress) that significantly undermines the robust operation of the system. Repeatedly opening and closing a DRAM row (RowHammer) or keeping a DRAM row open for a long…
Goal-oriented de novo molecule design, namely generating molecules with specific property or substructure constraints, is a crucial yet challenging task in drug discovery. Existing methods, such as Bayesian optimization and reinforcement…
As an emerging post-CMOS Field Effect Transistor, Magneto-Electric FETs (MEFETs) offer compelling design characteristics for logic and memory applications, such as high-speed switching, low power consumption, and non-volatility. In this…
Large-scale PDE simulations using high-order finite-element methods on unstructured meshes are an indispensable tool in science and engineering. The widely used open-source PETSc library offers an efficient representation of generic…
Recently, the Degrees-of-Freedom (DoF) region of multiple-input-single-output (MISO) networks with imperfect channel state information at the transmitter (CSIT) has attracted significant attentions. An achievable scheme is known as…
Writing magnetic bits by spin-orbit torques (SOTs) arising from spin Hall effect creates new possibilities for ultrafast and low-power magnetoresistive random access memory (MRAM). For perpendicular MRAM, an extra in-plane field is required…
In this paper, we propose a Junctionless (JL)/Accumulation Mode (AM) transistor with an access transistor (JL in series with JL/AM transistor) based capacitorless Dynamic Random Access Memory (1TDRAM) cell. The JL transistor overcomes the…
Zeroth-order (ZO) optimization has become increasingly popular and important in fine-tuning large language models (LLMs), especially on edge devices due to its ability to adjust the model to local data without the need for memory-intensive…
Stencil computations lie at the heart of many scientific and industrial applications. Unfortunately, stencil algorithms perform poorly on machines with cache based memory hierarchy, due to low re-use of memory accesses. This work shows that…
Recent reports on machine learning (ML) and machine vision (MV) devices have demonstrated the potentials of 2D materials and devices. Yet, scalable 2D devices are being challenged by contact resistance and Fermi Level Pinning (FLP), power…
In a Non-Orthogonal Unicast and Multicast (NOUM) transmission system, a multicast stream intended to all the receivers is superimposed in the power domain on the unicast streams. One layer of Successive Interference Cancellation (SIC) is…
Self-supervised learning (SSL) has shown impressive results in downstream classification tasks. However, there is limited work in understanding their failure modes and interpreting their learned representations. In this paper, we study the…
Deploying Large Language Models (LLMs) on resource-constrained edge devices faces critical bottlenecks in memory bandwidth and power consumption. While ternary quantization (e.g., BitNet b1.58) significantly reduces model size, its direct…
In modern Commercial Off-The-Shelf (COTS) multicore systems, each core can generate many parallel memory requests at a time. The processing of these parallel requests in the DRAM controller greatly affects the memory interference delay…
Considering a heterogeneous network (HetNet) system consisting of a macro tier overlaid with a second tier of small cells (SCs), this paper studies the mean square error (MSE) based precoding design to be employed by the macro base station…
We develop an unsupervised deep learning framework for real-time scalable and generalizable downlink beamforming in multi-user multiple-input single-output (MU-MISO) systems. The proposed semi-amortized lifted learning-to-optimize (SALLO)…
Aligning with the global mandates pushing towards advanced technologies with reduced resource consumption and environmental impacts, the sustainability of wireless networks becomes a significant concern in 6G systems. To address this…
Resistive memories have limited lifetime caused by limited write endurance and highly non-uniform write access patterns. Two main techniques to mitigate endurance-related memory failures are 1) wear-leveling, to evenly distribute the writes…
Phase change memory (PCM) has recently emerged as a promising technology to meet the fast growing demand for large capacity memory in computer systems, replacing DRAM that is impeded by physical limitations. Multi-level cell (MLC) PCM…