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This paper presents an approximate signed multiplier architecture that incorporates a sign-focused compressor, specifically designed for edge detection applications in machine learning and signal processing. The multiplier incorporates two…

Hardware Architecture · Computer Science 2025-10-28 L. Hemanth Krishna , Srinivasu Bodapati , Sreehari Veeramachaneni , BhaskaraRao Jammu , Noor Mahammad Sk

Systolic array accelerators execute CNNs with energy dominated by the switching activity of multiply accumulate (MAC) units. Although prior work exploits weight dependent MAC power for compression, existing methods often use global…

Hardware Architecture · Computer Science 2025-12-17 Jiaxun Fang , Grace Li Zhang , Shaoyi Huang

Bit-level sparsity in quantized deep neural networks (DNNs) offers significant potential for optimizing Multiply-Accumulate (MAC) operations. However, two key challenges still limit its practical exploitation. First, conventional bit-serial…

Hardware Architecture · Computer Science 2025-07-15 Feilong Qiaoyuan , Jihe Wang , Zhiyu Sun , Linying Wu , Yuanhua Xiao , Danghui Wang

This paper presents a novel attention-based algorithm for achieving adaptive computation called DACT, which, unlike existing ones, is end-to-end differentiable. Our method can be used in conjunction with many networks; in particular, we…

Artificial Intelligence · Computer Science 2020-05-25 Cristobal Eyzaguirre , Alvaro Soto

As the scaling of conventional CMOS-based technologies slows down, there is growing interest in alternative technologies that can improve performance or energy-efficiency. Superconducting circuits based on Josephson Junction (JJ) is an…

Hardware Architecture · Computer Science 2019-02-15 Swamit S. Tannu , Poulami Das , Michael L. Lewis , Robert Krick , Douglas M. Carmean , Moinuddin K. Qureshi

Dedicated accelerators are being designed to address the huge resource requirement of the deep neural network (DNN) applications. The power, performance and area (PPA) constraints limit the number of MACs available in these accelerators.…

Hardware Architecture · Computer Science 2021-02-25 Mahesh Chandra

General Matrix Multiply (GEMM) units, consisting of multiply-accumulate (MAC) arrays, perform bulk of the computation in deep learning (DL). Recent work has proposed a novel MAC design, Bit-Pragmatic (PRA), capable of dynamically exploiting…

Hardware Architecture · Computer Science 2025-01-03 Harideep Nair , Prabhu Vellaisamy , Tsung-Han Lin , Perry Wang , Shawn Blanton , John Paul Shen

Questing for learned lossy image coding (LIC) with superior compression performance and computation throughput is challenging. The vital factor behind it is how to intelligently explore Adaptive Neighborhood Information Aggregation (ANIA)…

Image and Video Processing · Electrical Eng. & Systems 2022-10-13 Ming Lu , Fangdong Chen , Shiliang Pu , Zhan Ma

The rapid updates in error-resilient applications along with their quest for high throughput have motivated designing fast approximate functional units for Field-Programmable Gate Arrays (FPGAs). Studies that proposed imprecise functional…

Hardware Architecture · Computer Science 2022-06-29 Zahra Ebrahimi , Muhammad Zaid , Mark Wijtvliet , Akash Kumar

Artificial intelligence (AI) is increasingly deployed in real-time and energy-constrained environments, driving demand for hardware platforms that can deliver high performance and power efficiency. While central processing units (CPUs) and…

Hardware Architecture · Computer Science 2026-01-28 Aybars Yunusoglu , Talha Coskun , Hiruna Vishwamith , Murat Isik , I. Can Dikmen

The ability to estimate joint parameters is essential for various applications in robotics and computer vision. In this paper, we propose CAPT: category-level articulation estimation from a point cloud using Transformer. CAPT uses an…

Computer Vision and Pattern Recognition · Computer Science 2024-02-28 Lian Fu , Ryoichi Ishikawa , Yoshihiro Sato , Takeshi Oishi

Exploration tasks are essential to many emerging robotics applications, ranging from search and rescue to space exploration. The planning problem for exploration requires determining the best locations for future measurements that will…

Hardware Architecture · Computer Science 2022-10-10 Keshav Gupta , Peter Zhi Xuan Li , Sertac Karaman , Vivienne Sze

Large language models (LLMs) are one of the most important killer computer applications. The recent algorithmic advancement proposes a fine-grained group-wise quantization for LLMs, which treats a small set (e.g., 64) of values in a tensor…

Hardware Architecture · Computer Science 2025-02-27 Weiming Hu , Haoyan Zhang , Cong Guo , Yu Feng , Renyang Guan , Zhendong Hua , Zihan Liu , Yue Guan , Minyi Guo , Jingwen Leng

In this study, we address the challenge of low-rank model compression in the context of in-memory computing (IMC) architectures. Traditional pruning approaches, while effective in model size reduction, necessitate additional peripheral…

Hardware Architecture · Computer Science 2025-02-13 Kang Eun Jeon , Johnny Rhe , Jong Hwan Ko

Matrix extensions have emerged as an essential feature in modern CPUs to address the surging demands of AI workloads. However, existing designs often incur substantial hardware and software design overhead. Tight coupling with the CPU…

Hardware Architecture · Computer Science 2026-04-14 Jinpeng Ye , Chongxi Wang , Wenqing Li , Bin Yuan , Shiyi Wang , Fenglu Zhang , Junyu Yue , Jianan Xie , Yunhao Ye , Haoyu Deng , Yingkun Zhou , Xin Cheng , Fuxin Zhang , Jian Wang

Attention for transformers is a critical workload that has recently received significant "attention" as a target for custom acceleration. Yet, while prior work succeeds in reducing attention's memory-bandwidth requirements, it creates load…

Hardware Architecture · Computer Science 2026-01-28 Nandeeka Nayak , Xinrui Wu , Toluwanimi O. Odemuyiwa , Michael Pellauer , Joel S. Emer , Christopher W. Fletcher

We present a full-stack optimization framework for accelerating inference of CNNs (Convolutional Neural Networks) and validate the approach with field-programmable gate arrays (FPGA) implementations. By jointly optimizing CNN models,…

Machine Learning · Computer Science 2019-05-03 Bradley McDanel , Sai Qian Zhang , H. T. Kung , Xin Dong

Large language models (LLMs) often leverage adapters, such as low-rank-based adapters, to achieve strong performance on downstream tasks. However, storing a separate adapter for each task significantly increases memory requirements, posing…

Machine Learning · Computer Science 2025-07-24 Taha Ceritli , Ondrej Bohdal , Mete Ozay , Jijoong Moon , Kyeng-Hun Lee , Hyeonmok Ko , Umberto Michieli

Recent advances in artificial intelligence, coupled with increasing data bandwidth requirements, in applications such as video processing and high-resolution sensing, have created a growing demand for high computational performance under…

Image and Video Processing · Electrical Eng. & Systems 2026-01-28 Himadri Singh Raghav , Sachin Maheshwari , Mike Smart , Patrick Foster , Alex Serb

State Space Models (SSMs) offer a promising alternative to transformers for long-sequence processing. However, their efficiency remains hindered by memory-bound operations, particularly in the prefill stage. While MARCA, a recent first…

Hardware Architecture · Computer Science 2026-04-10 Robin Geens , Arne Symons , Marian Verhelst