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Commercial Evaluation of Zero-Skipping MAC Design for Bit Sparsity Exploitation in DL Inference

Hardware Architecture 2025-01-03 v2

Abstract

General Matrix Multiply (GEMM) units, consisting of multiply-accumulate (MAC) arrays, perform bulk of the computation in deep learning (DL). Recent work has proposed a novel MAC design, Bit-Pragmatic (PRA), capable of dynamically exploiting bit sparsity. This work presents OzMAC (Omit-zero-MAC), a modified re-implementation of PRA, but extends beyond earlier works by performing rigorous post-synthesis evaluation against binary MAC design across multiple bitwidths and clock frequencies using TSMC N5 process node to assess commercial implementation potential. We demonstrate the existence of high bit sparsity in eight pretrained INT8 DL workloads and show that 8-bit OzMAC improves all three metrics of area, power, and energy significantly by 21%, 70%, and 28%, respectively. Similar improvements are achieved when scaling data precisions (4, 8, 16 bits) and clock frequencies (0.5 GHz, 1 GHz, 1.5 GHz). For the 8-bit OzMAC, scaling its frequency to normalize the throughput, it still achieves 30% improvement on both power and energy.

Keywords

Cite

@article{arxiv.2402.19376,
  title  = {Commercial Evaluation of Zero-Skipping MAC Design for Bit Sparsity Exploitation in DL Inference},
  author = {Harideep Nair and Prabhu Vellaisamy and Tsung-Han Lin and Perry Wang and Shawn Blanton and John Paul Shen},
  journal= {arXiv preprint arXiv:2402.19376},
  year   = {2025}
}

Comments

Pre-print version of the publication in VLSI-SoC 2024