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Related papers: Architectural and System Implications of CXL-enabl…

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MPI implementations commonly rely on explicit memory-copy operations, incurring overhead from redundant data movement and buffer management. This overhead notably impacts HPC workloads involving intensive inter-processor communication. In…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-10-17 Miryeong Kwon , Donghyun Gouk , Hyein Woo , Junhee Kim , Jinwoo Baek , Kyungkuk Nam , Sangyoon Ji , Jiseon Kim , Hanyeoreum Bae , Junhyeok Jang , Hyunwoo You , Junseok Moon , Myoungsoo Jung

This paper explores how Compute Express Link (CXL) can transform PCIe-based block storage into a scalable, byte-addressable working memory. We address the challenges of adapting block storage to CXL's memory-centric model by emphasizing…

Disaggregation and rack-scale systems have the potential of drastically decreasing TCO and increasing utilization of cloud datacenters, while maintaining performance. While the concept of organising resources in separate pools and…

Hardware Architecture · Computer Science 2018-01-12 Dimitris Syrivelis , Andrea Reale , Kostas Katrinis , Christian Pinto

The substantial memory requirements of Large Language Models (LLMs), particularly for long-context fine-tuning, have renewed interest in CPU offloading to augment limited GPU memory. However, as context lengths grow, relying on CPU memory…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-10-31 Yong-Cheng Liaw , Shuo-Han Chen

Datacenter applications often rely on remote procedure calls (RPCs) for fast, efficient, and secure communication. However, RPCs are slow, inefficient, and hard to use as they require expensive serialization and compression to communicate…

Distributed, Parallel, and Cluster Computing · Computer Science 2024-08-22 Suyash Mahar , Ehsan Hajyjasini , Seungjin Lee , Zifeng Zhang , Mingyao Shen , Steven Swanson

The continual increase of cores on server-grade CPUs raises demands on memory systems, which are constrained by limited off-chip pin and data transfer rate scalability. As a result, high-end processors typically feature lower memory…

Hardware Architecture · Computer Science 2025-11-18 Divya Kiran Kadiyala , Alexandros Daglis

As the memory channel count is confined by physical dimensions, memory expanders appear to be a promising approach to extending memory capacity and channels by augmenting the existing I/O interface (e.g., PCIe) with memory-semantic…

Hardware Architecture · Computer Science 2026-03-30 Younghoon Ko , Hyemin Park , Hyuk-Jae Lee , Hyokeun Lee

Memory disaggregation has recently been adopted in data centers to improve resource utilization, motivated by cost and sustainability. Recent studies on large-scale HPC facilities have also highlighted memory underutilization. A promising…

Distributed, Parallel, and Cluster Computing · Computer Science 2023-11-30 Jacob Wahlgren , Gabin Schieffer , Maya Gokhale , Ivy Peng

Datacenters of today have maintained the same architecture for decades using the server as the primary building block. However, this traditional approach suffers from under-utilization of its resources, often caused by over-allocating these…

Hardware Architecture · Computer Science 2024-02-21 Mohammad Ewais , Paul Chow

Despite the promise of alleviating the main memory bottleneck, and the existence of commercial hardware implementations, techniques for Near-Data Processing have seen relatively little real-world deployment. The idea has received renewed…

Operating Systems · Computer Science 2025-09-08 Zikai Liu , Jasmin Schult , Pengcheng Xu , Timothy Roscoe

Compute eXpress Link (CXL) is a promising technology for memory disaggregation and expansion. Especially, CXL makes it more effectively for large-capacity storage devices such as Solid State Drive (SSD) to be deployed in the memory pool.…

Hardware Architecture · Computer Science 2025-01-07 Yaohui Wang , Zicong Wang , Fanfeng Meng , Yanjing Wang , Yang Ou , Lizhou Wu , Wentao Hong , Xuran Ge , Jijun Cao

The growing demands in the training and inference of Large Language Models (LLMs) are accelerating the adoption of scale-up systems that extend server shared memory through the use of Compute Express Link (CXL)-based load/store…

Hardware Architecture · Computer Science 2026-04-01 Karan Pathak , David Atienza , Marina Zapater

Memory disaggregation (MD) allows for scalable and elastic data center design by separating compute (CPU) from memory. With MD, compute and memory are no longer coupled into the same server box. Instead, they are connected to each other via…

Databases · Computer Science 2022-07-08 Ruihong Wang , Jianguo Wang , Stratos Idreos , M. Tamer Özsu , Walid G. Aref

Concurrency has been a subject of study for more than 50 years. Still, many developers struggle to adapt their sequential code to be accessed concurrently. This need has pushed for generic solutions and specific concurrent data structures.…

Distributed, Parallel, and Cluster Computing · Computer Science 2019-11-06 Andreia Correia , Pedro Ramalhete , Pascal Felber

Engram conditional memory has emerged as a promising component for LLMs by decoupling static knowledge lookup from dynamic computation. Since Engram exhibits sparse access patterns and supports prefetching, its massive embedding tables are…

Hardware Architecture · Computer Science 2026-03-12 Ruiyang Ma , Teng Ma , Zhiyuan Su , Hantian Zha , Xinpeng Zhao , Xuchun Shang , Xingrui Yi , Zheng Liu , Zhu Cao , An Wu , Zhichong Dou , Ziqian Liu , Daikang Kuang , Guojie Luo

Pooling PCIe devices across multiple hosts offers a promising solution to mitigate stranded I/O resources, enhance device utilization, address device failures, and reduce total cost of ownership. The only viable option today are PCIe…

Disaggregating memory from compute offers the opportunity to better utilize stranded memory in cloud data centers. It is important to cache data in the compute nodes and maintain cache coherence across multiple compute nodes. However, the…

Databases · Computer Science 2026-01-14 Ruihong Wang , Jianguo Wang , Walid G. Aref

Memory-compute disaggregation promises transparent elasticity, high utilization and balanced usage for resources in data centers by physically separating memory and compute into network-attached resource "blades". However, existing designs…

Distributed, Parallel, and Cluster Computing · Computer Science 2021-10-22 Seung-seob Lee , Yanpeng Yu , Yupeng Tang , Anurag Khandelwal , Lin Zhong , Abhishek Bhattacharjee

Hardware based memory pooling enabled by interconnect standards like CXL have been gaining popularity amongst cloud providers and system integrators. While pooling memory resources has cost benefits, it comes at a penalty of increased…

Hardware Architecture · Computer Science 2024-06-24 Chandrahas Tirumalasetty , Narasimha Annapreddy

The expansion of context windows in large language models (LLMs) to multi-million tokens introduces severe memory and compute bottlenecks, particularly in managing the growing Key-Value (KV) cache. While Compute Express Link (CXL) enables…