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Related papers: Architectural and System Implications of CXL-enabl…

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This paper proposes TRAININGCXL that can efficiently process large-scale recommendation datasets in the pool of disaggregated memory while making training fault tolerant with low overhead. To this end, i) we integrate persistent memory…

Hardware Architecture · Computer Science 2023-01-23 Miryeong Kwon , Junhyeok Jang , Hanjin Choi , Sangwon Lee , Myoungsoo Jung

Compute Express Link (CXL) emerges as a solution for wide gap between computational speed and data communication rates among host and multiple devices. It fosters a unified and coherent memory space between host and CXL storage devices such…

High-Performance Computing (HPC) and Artificial Intelligence (AI) workloads typically demand substantial memory bandwidth and, to a degree, memory capacity. CXL memory expansion modules, also known as CXL "type-3" devices, enable…

Operating Systems · Computer Science 2024-12-18 Rohit Sehgal , Vishal Tanna , Vinicius Petrucci , Anil Godbole

Emerging interconnects, such as CXL and NVLink, have been integrated into the intra-host topology to scale more accelerators and facilitate efficient communication between them, such as GPUs. To keep pace with the accelerator's growing…

Distributed, Parallel, and Cluster Computing · Computer Science 2026-01-19 Xu Zhang , Ke Liu , Yisong Chang , Ke Zhang , Mingyu Chen

Compute and memory are tightly coupled within each server in traditional datacenters. Large-scale datacenter operators have identified this coupling as a root cause behind fleet-wide resource underutilization and increasing Total Cost of…

Distributed, Parallel, and Cluster Computing · Computer Science 2023-05-09 Hasan Al Maruf , Mosharaf Chowdhury

Current HPC systems provide memory resources that are statically configured and tightly coupled with compute nodes. However, workloads on HPC systems are evolving. Diverse workloads lead to a need for configurable memory resources to…

Distributed, Parallel, and Cluster Computing · Computer Science 2023-03-23 Jacob Wahlgren , Maya Gokhale , Ivy B. Peng

This work introduces a GPU storage expansion solution utilizing CXL, featuring a novel GPU system design with multiple CXL root ports for integrating diverse storage media (DRAMs and/or SSDs). We developed and siliconized a custom CXL…

Memory disaggregation can potentially allow memory-optimized range indexes such as B+-trees to scale beyond one machine while attaining high hardware utilization and low cost. Designing scalable indexes on disaggregated memory, however, is…

Databases · Computer Science 2024-05-24 Baotong Lu , Kaisong Huang , Chieh-Jan Mike Liang , Tianzheng Wang , Eric Lo

In GPU graph analytics, the use of external memory such as the host DRAM and solid-state drives is a cost-effective approach to processing large graphs beyond the capacity of the GPU onboard memory. This paper studies the use of Compute…

Disaggregated memory is a promising approach that addresses the limitations of traditional memory architectures by enabling memory to be decoupled from compute nodes and shared across a data center. Cloud platforms have deployed such…

Distributed, Parallel, and Cluster Computing · Computer Science 2023-06-21 Nan Ding , Pieter Maris , Hai Ah Nam , Taylor Groves , Muaaz Gul Awan , LeAnn Lindsey , Christopher Daley , Oguz Selvitopi , Leonid Oliker , Nicholas Wright , Samuel Williams

Transaction processing systems are the crux for modern data-center applications, yet current multi-node systems are slow due to network overheads. This paper advocates for Compute Express Link (CXL) as a network alternative, which enables…

Hardware Architecture · Computer Science 2025-07-24 Zhao Wang , Yiqi Chen , Cong Li , Dimin Niu , Tianchan Guan , Zhaoyang Du , Xingda Wei , Guangyu Sun

Emerging Compute Express Link (CXL) enables cost-efficient memory expansion beyond the local DRAM of processors. While its CXL$.$mem protocol provides minimal latency overhead through an optimized protocol stack, frequent CXL memory…

CXL (Compute Express Link) enables multiple hosts to share byte-addressable memory with hardware cache coherence, but no existing filesystem exploits this for lock-free multi-host coordination. We present DaxFS, a Linux filesystem for CXL…

Operating Systems · Computer Science 2026-04-03 Cong Wang , Yiwei Yang , Yusheng Zheng

The rapid increase in LLM model sizes and the growing demand for long-context inference have made memory a critical bottleneck in GPU-accelerated serving systems. Although high-bandwidth memory (HBM) on GPUs offers fast access, its limited…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-12-01 Xinjun Yang , Qingda Hu , Junru Li , Feifei Li , Yicong Zhu , Yuqi Zhou , Qiuru Lin , Jian Dai , Yang Kong , Jiayu Zhang , Guoqiang Xu , Qiang Liu

The "Disaggregated Server" concept has been proposed for datacenters where the same type server resources are aggregated in their respective pools, for example a compute pool, memory pool, network pool, and a storage pool. Each server is…

Distributed, Parallel, and Cluster Computing · Computer Science 2015-03-09 Bulent Abali , Richard J. Eickemeyer , Hubertus Franke , Chung-Sheng Li , Marc A. Taubenblatt

Rollout-training disaggregation is emerging as the standard architecture for Reinforcement Learning (RL) post-training, where memory-bound rollout and compute-bound training are physically disaggregated onto purpose-built clusters to…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-12-16 Tianyuan Wu , Lunxi Cao , Yining Wei , Wei Gao , Yuheng Zhao , Dakai An , Shaopan Xiong , Zhiqiang Lv , Ju Huang , Siran Yang , Yinghao Yu , Jiamang Wang , Lin Qu , Wei Wang

PCIe devices, such as SSDs and GPUs, are pivotal in modern data centers, and their value is set to grow amidst the emergence of AI and large models. However, these devices face onboard DRAM shortage issue due to internal space limitation,…

Hardware Architecture · Computer Science 2024-06-05 Jiapin Wang , Xiangping Zhang , Chenlei Tang , Xiang Chen , Tao Lu

Disaggregation is an ongoing trend to increase flexibility in datacenters. With interconnect technologies like CXL, pools of CPUs, accelerators, and memory can be connected via a datacenter fabric. Applications can then pick from those…

Distributed, Parallel, and Cluster Computing · Computer Science 2024-06-17 Nils Asmussen , Michael Roitzsch

We propose the design and an implementation of a bulk-parallel external memory priority queue to take advantage of both shared-memory parallelism and high external memory transfer speeds to parallel disks. To achieve higher performance by…

Data Structures and Algorithms · Computer Science 2015-04-03 Timo Bingmann , Thomas Keh , Peter Sanders

Modern AI workloads such as large language models (LLMs) and retrieval-augmented generation (RAG) impose severe demands on memory, communication bandwidth, and resource flexibility. Traditional GPU-centric architectures struggle to scale…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-07-15 Myoungsoo Jung