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Related papers: Non-interfering On-line and In-field SoC Testing

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Single-event upset (SEU) fault tolerance for systems-on-chip (SoCs) in radiation-heavy environments is often addressed by architectural fault-tolerance approaches protecting individual SoC components (e.g., cores, memories) in isolation.…

Hardware Architecture · Computer Science 2026-03-30 Michael Rogenmoser , Philippe Sauter , Chen Wu , Angelo Garofalo , Luca Benini

The advanced complex electronic systems increasingly demand safer and more secure hardware parts. Correspondingly, fault injection became a major verification milestone for both safety- and security-critical applications. However, fault…

Hardware Architecture · Computer Science 2021-03-10 Ahmet Cagri Bagbaba , Maksim Jenihhin , Raimund Ubar , Christian Sauer

This paper presents a detailed evaluation of the efficiency of software-only techniques to mitigate SEU and SET in microprocessors. A set of well-known rules is presented and implemented automatically to transform an unprotected program…

Hardware Architecture · Computer Science 2023-10-02 Jose Rodrigo Azambuja , Fernando Sousa , Lucas Rosa , Fernanda Lima Kastensmidt

Very deep submicron and nanometer technologies have increased notably integrated circuit (IC) sensitiveness to radiation. Soft errors are currently appearing into ICs working at earth surface. Hardened circuits are currently required in…

Hardware Architecture · Computer Science 2011-11-09 Celia Lopez-Ongil , Mario Garcia-Valderas , Marta Portela-Garcia , Luis Entrena-Arrontes

Cyber-Physical Systems (CPSs), such as Unmanned Aerial Vehicles (UAVs), use System-on-Chip (SoC) based computing platforms to perform multiple complex tasks in safety-critical applications that require a highly dependable operation. Due to…

Hardware Architecture · Computer Science 2023-03-06 Foisal Ahmed , Maksim Jenihhin

Modern Systems-on-Chip (SoCs) incorporate built-in self-test (BIST) modules deeply integrated into the device's intellectual property (IP) blocks. Such modules handle hardware faults and defects during device operation. As such, BIST…

Hardware Architecture · Computer Science 2025-02-18 Saleh Mulhem , Christian Ewert , Andrija Neskovic , Amrit Sharma Poudel , Christoph Hübner , Mladen Berekovic , Rainer Buchty

A single event upset (SEU) is a critical soft error that occurs in semiconductor devices on exposure to ionising particles from space environments. SEUs cause bit flips in the memory component of semiconductors. This creates a multitude of…

Machine Learning · Computer Science 2023-10-10 Archit Gupta , Chong Yock Eng , Deon Lim Meng Wee , Rashna Analia Ahmed , See Min Sim

The hardware computing landscape is changing. What used to be distributed systems can now be found on a chip with highly configurable, diverse, specialized and general purpose units. Such Systems-on-a-Chip (SoC) are used to control today's…

Cryptography and Security · Computer Science 2023-07-06 Ali Shoker , Paulo Esteves Verissimo , Marcus Völp

Reliability has been a major concern in embedded systems. Higher transistor density and lower voltage supply increase the vulnerability of embedded systems to soft errors. A Single Event Upset (SEU), which is also called a soft error, can…

Hardware Architecture · Computer Science 2024-05-21 Bing Xue , Mark Zwolinski

The AMD UltraScale+ XCZU9EG device is a Multi-Processor System-on-Chip (MPSoC) with embedded Programmable Logic (PL) that excels in many Edge (e.g., automotive or avionics) and Cloud (e.g., data centres) terrestrial applications. However,…

The computational power of High-Performance Computing (HPC) systems is constantly increasing, however, their input/output (IO) performance grows relatively slowly, and their storage capacity is also limited. This unbalance presents…

Handling faults is a growing concern in HPC. In future exascale systems, it is projected that silent undetected errors will occur several times a day, increasing the occurrence of corrupted results. In this article, we propose SEDAR, which…

Distributed, Parallel, and Cluster Computing · Computer Science 2020-07-29 Diego Montezanti , Enzo Rucci , Armando De Giusti , Marcelo Naiouf , Dolores Rexachs , Emilio Luque

Recent embedded systems are designed with high-performance System-on-Chips (SoCs) to satisfy the computational needs of complex applications widely used in real life, such as airplane controllers, autonomous driving automobiles, medical…

Distributed, Parallel, and Cluster Computing · Computer Science 2021-01-01 Seyed Mehdi Hosseini Motlagh

Designing integrated circuits in radiation environments such as the High Luminosity LHC (HL-LHC) is challenging. Integrated circuits will be exposed to radiation-induced Single Event Effects (SEE). In deep sub-micron technology devices, the…

Instrumentation and Detectors · Physics 2022-02-16 D. Boumediene , F. Jouve , D. Lambert , R. Madar , S. Manen , O. Perrin , L. Royer , A. Soulier , R. Vandaele

Integrating Artificial Intelligence (AI) technology in electric vehicles (EV) introduces unique challenges for safety assurance, particularly within the framework of ISO 26262, which governs functional safety in the automotive domain.…

Software Engineering · Computer Science 2025-09-04 Martin Skoglund , Fredrik Warg , Aria Mirzai , Anders Thorsen , Karl Lundgren , Peter Folkesson , Bastian Havers-zulka

In-field test of processor-based devices is a must when considering safety-critical systems (e.g., in robotics, aerospace, and automotive applications). During in-field testing, different solutions can be adopted, depending on the specific…

Hardware Architecture · Computer Science 2021-09-09 Juan-David Guerrero-Balaguera , Josie E. Rodriguez Condia , Matteo Sonza Reorda

Ultra Deep-Sub-Micron CMOS chips have to function correctly and reliably, not only during their early post-fabrication life, but also for their entire life span. In this paper, we present an architectural-level in-field repair technique.…

Hardware Architecture · Computer Science 2015-10-07 Massoud Mokhtarpour Ghahroodi , Mark Zwolinski

Errors due to hardware or low level software problems, if detected, can be fixed by various schemes, such as recomputation from a checkpoint. Silent errors are errors in application state that have escaped low-level error detection. At…

Numerical Analysis · Computer Science 2018-01-08 Austin R. Benson , Sven Schmit , Robert Schreiber

In hardware accelerators used in data centers and safety-critical applications, soft errors and resultant silent data corruption significantly compromise reliability, particularly when upsets occur in control-flow operations, leading to…

Hardware Architecture · Computer Science 2025-05-09 Tomonari Tanaka , Takumi Uezono , Kohei Suenaga , Masanori Hashimoto

We present systematic and efficient solutions for both observability enhancement and root-cause diagnosis of post-silicon System-on-Chips (SoCs) validation with diverse usage scenarios. We model specification of interacting flows in typical…

Hardware Architecture · Computer Science 2021-02-10 Debjit Pal , Shobha Vasudevan
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