English
Related papers

Related papers: DiP: A Scalable, Energy-Efficient Systolic Array f…

200 papers

As AI-based applications become pervasive, CPU vendors are starting to incorporate matrix engines within the datapath to boost efficiency. Systolic arrays have been the premier architectural choice as matrix engines in offload accelerators.…

Hardware Architecture · Computer Science 2021-10-06 Geonhwa Jeong , Eric Qin , Ananda Samajdar , Christopher J. Hughes , Sreenivas Subramoney , Hyesoon Kim , Tushar Krishna

Data center networks leverage multiple parallel paths connecting end host pairs to offer high bisection bandwidth for cluster computing applications. However, state of the art distributed multi-pathing protocols such as Equal Cost Multipath…

Networking and Internet Architecture · Computer Science 2013-07-30 Wenzhi Cui , Chen Qian

Transformers have revolutionized deep learning and generative modeling, enabling advancements in natural language processing tasks. However, the size of transformer models is increasing continuously, driven by enhanced capabilities across…

Hardware Architecture · Computer Science 2025-02-18 Harsh Sharma , Pratyush Dhingra , Janardhan Rao Doppa , Umit Ogras , Partha Pratim Pande

Compute-In-Memory (CiM) is a promising solution to accelerate Deep Neural Networks (DNNs) as it can avoid energy-intensive DNN weight movement and use memory arrays to perform low-energy, high-density computations. These benefits have…

Hardware Architecture · Computer Science 2024-11-01 Tanner Andrulis , Joel S. Emer , Vivienne Sze

Battery-less technology evolved to replace battery usage in space, deep mines, and other environments to reduce cost and pollution. Non-volatile memory (NVM) based processors were explored for saving the system state during a power failure.…

Hardware Architecture · Computer Science 2023-05-18 SatyaJaswanth Badri , Mukesh Saini , Neeraj Goel

Distributed deep learning (DDL) systems strongly depend on network performance. Current electronic packet switched (EPS) network architectures and technologies suffer from variable diameter topologies, low-bisection bandwidth and…

Distributed, Parallel, and Cluster Computing · Computer Science 2023-02-27 Alessandro Ottino , Joshua Benjamin , Georgios Zervas

Myriad of graph-based algorithms in machine learning and data mining require parsing relational data iteratively. These algorithms are implemented in a large-scale distributed environment in order to scale to massive data sets. To…

Distributed, Parallel, and Cluster Computing · Computer Science 2017-10-17 Yanfeng Zhang , Qixin Gao , Lixin Gao , Cuirong Wang

The combination of Winograd's algorithm and systolic array architecture has demonstrated the capability of improving DSP efficiency in accelerating convolutional neural networks (CNNs) on FPGA platforms. However, handling arbitrary…

Hardware Architecture · Computer Science 2021-07-12 Xinheng Liu , Yao Chen , Cong Hao , Ashutosh Dhar , Deming Chen

Massive MIMO is a cornerstone of next-generation wireless communication, offering significant gains in capacity, reliability, and energy efficiency. However, to meet emerging demands such as high-frequency operation, wide bandwidths,…

Signal Processing · Electrical Eng. & Systems 2026-01-21 Ali Rasteh , Andrew Hennessee , Ishaan Shivhare , Siddharth Garg , Sundeep Rangan , Brandon Reagen

Accelerating the inference of a trained DNN is a well studied subject. In this paper we switch the focus to the training of DNNs. The training phase is compute intensive, demands complicated data communication, and contains multiple levels…

Distributed, Parallel, and Cluster Computing · Computer Science 2017-06-09 Yuanfang Li , Ardavan Pedram

Advances in hybrid bonding and packaging have driven growing interest in 3D DRAM-stacked accelerators with higher memory bandwidth and capacity. As LLMs scale to hundreds of billions or trillions of parameters, distributed inference across…

With the development of deep neural network (DNN) enabled applications, achieving high hardware resource efficiency on diverse workloads is non-trivial in heterogeneous computing platforms. Prior works discuss dedicated architectures to…

Hardware Architecture · Computer Science 2026-04-14 Xingzhen Chen , Jinming Zhuang , Zhuoping Yang , Shixin Ji , Sarah Schultz , Zheng Dong , Weisong Shi , Peipei Zhou

The growth in data storage capacity and the increasing demands for high performance have created several challenges for concurrent indexing structures. One promising solution is learned indexes, which use a learning-based approach to fit…

Databases · Computer Science 2023-09-06 Jiake Ge , Huanchen Zhang , Boyu Shi , Yuanhui Luo , Yunda Guo , Yunpeng Chai , Yuxing Chen , Anqun Pan

Systolic Arrays are one of the most popular compute substrates within Deep Learning accelerators today, as they provide extremely high efficiency for running dense matrix multiplications. However, the research community lacks tools to…

Distributed, Parallel, and Cluster Computing · Computer Science 2019-02-05 Ananda Samajdar , Yuhao Zhu , Paul Whatmough , Matthew Mattina , Tushar Krishna

Increased reliance on graphics processing units (GPUs) for high-intensity computing tasks raises challenges regarding energy consumption. To address this issue, dynamic voltage and frequency scaling (DVFS) has emerged as a promising…

Performance · Computer Science 2024-07-19 Qiang Wang , Laiyi Li , Weile Luo , Yijia Zhang , Bingqiang Wang

In this paper, we present a dynamically reconfigurable hardware accelerator called FADES (Fused Architecture for DEnse and Sparse matrices). The FADES design offers multiple configuration options that trade off parallelism and complexity…

Hardware Architecture · Computer Science 2023-04-18 Jose Nunez-Yanez , Andres Otero , Eduardo de la Torre

Near-Data-Processing (NDP) architectures present a promising way to alleviate data movement costs and can provide significant performance and energy benefits to parallel applications. Typically, NDP architectures support several NDP units,…

Processing-in-memory (PIM) is a promising computing paradigm to tackle the "memory wall" challenge. However, PIM system-level benefits over traditional von Neumann architecture can be reduced when the memory array cannot fully store all the…

Hardware Architecture · Computer Science 2025-03-03 Peilin Chen , Xiaoxuan Yang

The performance gains obtained by large language models (LLMs) are closely linked to their substantial computational and memory requirements. Quantized LLMs offer significant advantages with extremely quantized models, motivating the…

Hardware Architecture · Computer Science 2026-04-07 Ahmed J. Abdelmaksoud , Cristian Sestito , Shiwei Wang , Themis Prodromakis

Large multimodal models (LMMs) have demonstrated excellent capabilities in both understanding and generation tasks with various modalities. While these models can accept flexible combinations of input data, their training efficiency suffers…

Distributed, Parallel, and Cluster Computing · Computer Science 2026-03-24 Zhenliang Xue , Hanpeng Hu , Xing Chen , Yimin Jiang , Yixin Song , Zeyu Mi , Yibo Zhu , Daxin Jiang , Yubin Xia , Haibo Chen
‹ Prev 1 4 5 6 7 8 10 Next ›