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Autonomous robots require efficient on-device learning to adapt to new environments without cloud dependency. For this edge training, Microscaling (MX) data types offer a promising solution by combining integer and floating-point…

Hardware Architecture · Computer Science 2025-12-16 Stef Cuyckens , Xiaoling Yi , Nitish Satya Murthy , Chao Fang , Marian Verhelst

The increasing computational and memory demands of large language models (LLMs) necessitate innovative approaches to optimize resource usage without compromising performance. This paper leverages microscaling floating-point formats, a novel…

Neural and Evolutionary Computing · Computer Science 2025-10-03 Marco Cococcioni , Dario Pagani , Federico Rossi

The Graphic Processing Unit (GPU) has evolved into a powerful and flexible processor. The latest graphic processors provide fully programmable vertex and pixel processing units that support vector operations up to single floating-point…

Hardware Architecture · Computer Science 2007-05-23 Guillaume Da Graçca , David Defour

Using fewer bits to represent model parameters and related tensors during pre-training has become a required technique for improving GPU efficiency without sacrificing accuracy. Microscaling (MX) formats introduced in NVIDIA Blackwell…

Machine Learning · Computer Science 2025-08-20 Asit Mishra , Dusan Stosic , Simon Layton , Paulius Micikevicius

Floating point multiplication is one of the crucial operations in many application domains such as image processing, signal processing etc. But every application requires different working features. Some need high precision, some need low…

Hardware Architecture · Computer Science 2020-12-08 S. Arish , R. K. Sharma

We propose a scheme for reduced-precision representation of floating point data on a continuum between IEEE-754 floating point types. Our scheme enables the use of lower precision formats for a reduction in storage space requirements and…

Mathematical Software · Computer Science 2017-01-31 Andrew Anderson , David Gregg

In modern low-power embedded platforms, floating-point (FP) operations emerge as a major contributor to the energy consumption of compute-intensive applications with large dynamic range. Experimental evidence shows that 50% of the energy…

Hardware Architecture · Computer Science 2017-11-29 Giuseppe Tagliavini , Stefan Mach , Davide Rossi , Andrea Marongiu , Luca Benini

Reduced-precision data formats are crucial for cost-effective serving of large language models (LLMs). While numerous reduced-precision formats have been introduced thus far, they often require intrusive modifications to the software…

Machine Learning · Computer Science 2025-10-17 Jungi Lee , Junyong Park , Soohyun Cha , Jaehoon Cho , Jaewoong Sim

As the demand for deep learning grows, cost reduction through quantization has become essential for both training and inference. In 2022, the Open Compute Project (OCP) consortium standardized narrow precision formats for deep learning,…

Hardware Architecture · Computer Science 2026-05-26 Dahoon Park , Jahyun Koo , Sangwoo Hwang , Jaeha Kung

A number of companies recently worked together to release the new Open Compute Project MX standard for low-precision computation, aimed at efficient neural network implementation. In this paper, we describe and evaluate the first…

Hardware Architecture · Computer Science 2024-07-02 Ebby Samson , Naveen Mellempudi , Wayne Luk , George A. Constantinides

Model quantization represents both parameters (weights) and intermediate values (activations) in a more compact format, thereby directly reducing both computational and memory cost in hardware. The quantization of recent large language…

Hardware Architecture · Computer Science 2024-04-22 Jianyi Cheng , Cheng Zhang , Zhewen Yu , Christos-Savvas Bouganis , George A. Constantinides , Yiren Zhao

As cutting-edge large language models (LLMs) continue to transform various industries, their fast-growing model size and sequence length have led to memory traffic and capacity challenges. Recently, AMD, Arm, Intel, Meta, Microsoft, NVIDIA,…

Hardware Architecture · Computer Science 2024-12-31 Yun-Chen Lo , Gu-Yeon Wei , David Brooks

Emerging continual learning applications necessitate next-generation neural processing unit (NPU) platforms to support both training and inference operations. The promising Microscaling (MX) standard enables narrow bit-widths for inference…

Hardware Architecture · Computer Science 2026-03-13 Stef Cuyckens , Xiaoling Yi , Robin Geens , Joren Dumoulin , Martin Wiesner , Chao Fang , Marian Verhelst

There is a growing interest in the use of reduced-precision arithmetic, exacerbated by the recent interest in artificial intelligence, especially with deep learning. Most architectures already provide reduced-precision capabilities (e.g.,…

Hardware Architecture · Computer Science 2022-12-09 Olivier Sentieys , Daniel Menard

In this paper, we propose an architecture/methodology for making FPGAs suitable for integer as well as variable precision floating point multiplication. The proposed work will of great importance in applications which requires variable…

Hardware Architecture · Computer Science 2007-11-19 Himanshu Thapliyal , Hamid R. Arabnia , Rajnish Bajpai , Kamal K. Sharma

Modern programmable digital signal processing relies on floating-point numbers for their ease of use. Fixed-point number formats have the potential to save resources and improve execution time, but realising this potential burdens the…

Programming Languages · Computer Science 2024-03-12 Agathe Herrou , Florent de Dinechin , Stéphane Letz , Yann Orlarey , Anastasia Volkova

Post-training quantization (PTQ) is a powerful technique for model compression, reducing the numerical precision in neural networks without additional training overhead. Recent works have investigated adopting 8-bit floating-point…

Computer Vision and Pattern Recognition · Computer Science 2024-07-08 Shivam Aggarwal , Hans Jakob Damsgaard , Alessandro Pappalardo , Giuseppe Franco , Thomas B. Preußer , Michaela Blott , Tulika Mitra

Existing low-bit Microscaling (MX) formats, such as MXFP4, often suffer from substantial accuracy degradation due to the use of a shared scaling factor with the Power-of-Two format. In this work, we explore strategies that introduce minimal…

Hardware Architecture · Computer Science 2026-01-29 Weiming Hu , Zihan Zhang , Haoyan Zhang , Chen Zhang , Cong Guo , Yu Feng , Tianchi Hu , Guanglin Li , Guipeng Hu , Junsong Wang , Jingwen Leng

ExaScale systems will be a key driver for simulations that are essential for advance of science and economic growth. We aim to present a new concept of microprocessor for floating-point computations useful for being a basic building block…

Hardware Architecture · Computer Science 2019-02-19 Elisardo Antelo

As large language models (LLMs) grow in parameter size and context length, computation precision has been reduced from 16-bit to 4-bit to improve inference efficiency. However, this reduction causes accuracy degradation due to activation…

Artificial Intelligence · Computer Science 2025-06-02 Janghwan Lee , Jiwoong Park , Jinseok Kim , Yongjik Kim , Jungju Oh , Jinwook Oh , Jungwook Choi
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