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We propose the Sparse Abstract Machine (SAM), an abstract machine model for targeting sparse tensor algebra to reconfigurable and fixed-function spatial dataflow accelerators. SAM defines a streaming dataflow abstraction with sparse…

Hardware Architecture · Computer Science 2023-03-27 Olivia Hsu , Maxwell Strange , Ritvik Sharma , Jaeyeon Won , Kunle Olukotun , Joel Emer , Mark Horowitz , Fredrik Kjolstad

Accelerating finite automata processing is critical for advancing real-time analytic in pattern matching, data mining, bioinformatics, intrusion detection, and machine learning. Recent in-memory automata accelerators leveraging SRAMs and…

Hardware Architecture · Computer Science 2021-12-02 Yi Huang , Zhiyu Chen , Dai Li , Kaiyuan Yang

A key proficiency an autonomous mobile robot must have to perform high-level tasks is a strong understanding of its environment. This involves information about what types of objects are present, where they are, what their spatial extend…

Deep neural networks are a promising solution for applications that solve problems based on learning data sets. DNN accelerators solve the processing bottleneck as a domain-specific processor. Like other hardware solutions, there must be…

Hardware Architecture · Computer Science 2022-11-08 Midia Reshadi , David Gregg

Tensor computations, with matrix multiplication being the primary operation, serve as the fundamental basis for data analysis, physics, machine learning, and deep learning. As the scale and complexity of data continue to grow rapidly, the…

Hardware Architecture · Computer Science 2024-10-24 Qizhe Wu , Yuchen Gui , Zhichen Zeng , Xiaotian Wang , Huawen Liang , Xi Jin

Designing effective architectures is one of the key factors behind the success of deep neural networks. Existing deep architectures are either manually designed or automatically searched by some Neural Architecture Search (NAS) methods.…

Computer Vision and Pattern Recognition · Computer Science 2021-02-23 Yong Guo , Yin Zheng , Mingkui Tan , Qi Chen , Zhipeng Li , Jian Chen , Peilin Zhao , Junzhou Huang

The rapid growth of large-language models (LLMs) is driving a new wave of specialized hardware for inference. This paper presents the first workload-centric, cross-architectural performance study of commercial AI accelerators, spanning…

Hardware Architecture · Computer Science 2025-06-10 Amit Sharma

We propose DFModel, a modeling framework for mapping dataflow computation graphs onto large-scale systems. Mapping a workload to a system requires optimizing dataflow mappings at various levels, including the inter-chip (between chips)…

Hardware Architecture · Computer Science 2024-12-24 Sho Ko , Nathan Zhang , Olivia Hsu , Ardavan Pedram , Kunle Olukotun

Benefiting from the self-attention mechanism, Transformer models have attained impressive contextual comprehension capabilities for lengthy texts. The requirements of high-throughput inference arise as the large language models (LLMs)…

Hardware Architecture · Computer Science 2024-07-16 Huizheng Wang , Jiahao Fang , Xinru Tang , Zhiheng Yue , Jinxi Li , Yubin Qin , Sihan Guan , Qize Yang , Yang Wang , Chao Li , Yang Hu , Shouyi Yin

General matrix multiplication (GEMM) on spatial accelerators is highly sensitive to mapping choices in both execution efficiency and energy consumption. However, the mapping space exhibits combinatorial explosion, which makes it extremely…

Hardware Architecture · Computer Science 2026-03-24 Wulve Yang , Hailong Zou , Rui Zhou , Jionghao Zhang , Qiang Li , Gang Li , Yi Zhan , Shushan Qiao

Neural-based motion planning methods have achieved remarkable progress for robotic manipulators, yet a fundamental challenge lies in simultaneously accounting for both the robot's physical shape and the surrounding environment when…

Robotics · Computer Science 2025-09-16 Kai Chen , Zhihai Bi , Guoyang Zhao , Chunxin Zheng , Yulin Li , Hang Zhao , Jun Ma

Content addressable memory (CAM) stands out as an efficient hardware solution for memory-intensive search operations by supporting parallel computation in memory. However, developing a CAM-based accelerator architecture that achieves…

Hardware Architecture · Computer Science 2024-03-11 Mengyuan Li , Shiyi Liu , Mohammad Mehdi Sharifi , X. Sharon Hu

Simultaneous Localization and Mapping (SLAM) estimates agents' trajectories and constructs maps, and localization is a fundamental kernel in autonomous machines at all computing scales, from drones, AR, VR to self-driving cars. In this…

Hardware Architecture · Computer Science 2022-04-18 Qiang Liu , Zishen Wan , Bo Yu , Weizhuang Liu , Shaoshan Liu , Arijit Raychowdhury

High-performance sparse matrix-matrix (SpMM) multiplication is paramount for science and industry, as the ever-increasing sizes of data prohibit using dense data structures. Yet, existing hardware, such as Tensor Cores (TC), is ill-suited…

Distributed, Parallel, and Cluster Computing · Computer Science 2024-08-22 Patrik Okanovic , Grzegorz Kwasniewski , Paolo Sylos Labini , Maciej Besta , Flavio Vella , Torsten Hoefler

GPU-accelerated Self-Organizing Map (SOM) implementations are among the most competitive options for large-scale SOM analysis, but growing dataset sizes increasingly challenge their practical use because workloads no longer fit cleanly…

Distributed, Parallel, and Cluster Computing · Computer Science 2026-04-30 Tony Xu , Sarah Klamt , Katherine Turner , Anne Brustle , Felix Marsh-Wakefield , Givanna Putri

The rapidly-changing deep learning landscape presents a unique opportunity for building inference accelerators optimized for specific datacenter-scale workloads. We propose Full-stack Accelerator Search Technique (FAST), a hardware…

Machine Learning · Computer Science 2022-02-02 Dan Zhang , Safeen Huda , Ebrahim Songhori , Kartik Prabhu , Quoc Le , Anna Goldie , Azalia Mirhoseini

Large language models (LLMs) have demonstrated exceptional proficiency in understanding and generating human language, but efficient inference on resource-constrained embedded devices remains challenging due to large model sizes and…

Hardware Architecture · Computer Science 2025-07-15 Weihong Xu , Haein Choi , Po-kai Hsu , Shimeng Yu , Tajana Rosing

Processing in-memory (PIM) is promising to accelerate neural networks (NNs) because it minimizes data movement and provides large computational parallelism. Similar to machine learning accelerators, application mapping, which determines the…

Hardware Architecture · Computer Science 2024-07-02 Xuan Wang , Minxuan Zhou , Tajana Rosing

Ternary weight quantization (e.g., BitNet b1.58) offers a promising path to mitigate the memory bandwidth bottleneck in Large Language Model (LLM) inference. However, conventional compute platforms lack native support for ternary-weight…

Hardware Architecture · Computer Science 2026-04-29 Robin Geens , Joran Heldens , Joren Dumoulin , Marian Verhelst

Large language models (LLMs) exhibit memory-intensive behavior during decoding, making it a key bottleneck in LLM inference. To accelerate decoding execution, hybrid-bonding-based 3D-DRAM has been adopted in LLM accelerators. While this…

Hardware Architecture · Computer Science 2026-04-10 Cong Li , Chenhao Xue , Yi Ren , Xiping Dong , Yu Cheng , Yinbo Hu , Fujun Bai , Yixin Guo , Xiping Jiang , Qiang Wu , Zhi Yang , Zhe Cheng , Yuan Xie , Guangyu Sun