English
Related papers

Related papers: An Efficient Algorithm for Modulus Operation and I…

200 papers

Number Theoretic Transform (NTT) is an essential mathematical tool for computing polynomial multiplication in promising lattice-based cryptography. However, costly division operations and complex data dependencies make efficient and…

Hardware Architecture · Computer Science 2023-04-25 Jingyao Zhang , Mohsen Imani , Elaheh Sadredini

We show a new algorithm and its implementation for multiplying bit-polynomials of large degrees. The algorithm is based on evaluating polynomials at a specific set comprising a natural set for evaluation with additive FFT and a high order…

Symbolic Computation · Computer Science 2018-04-02 Ming-Shing Chen , Chen-Mou Cheng , Po-Chun Kuo , Wen-Ding Li , Bo-Yin Yang

We give an $O(N\cdot \log N\cdot 2^{O(\log^*N)})$ algorithm for multiplying two $N$-bit integers that improves the $O(N\cdot \log N\cdot \log\log N)$ algorithm by Sch\"{o}nhage-Strassen. Both these algorithms use modular arithmetic.…

Symbolic Computation · Computer Science 2008-09-19 Anindya De , Piyush P Kurur , Chandan Saha , Ramprasad Saptharishi

In the field of cryptography till date the 2-byte in 1-clock is the best known RC4 hardware design [1], while 1-byte in 1-clock [2], and the 1-byte in 3 clocks [3][4] are the best known implementation. The design algorithm in[2] considers…

Hardware Architecture · Computer Science 2014-01-14 Rourab Paul , Amlan Chakrabarti , Ranjan Ghosh

To address the privacy protection problem in cloud computing, privacy enhancement techniques such as the Paillier additive homomorphism algorithm are receiving widespread attention. Paillier algorithm allows addition and scalar…

Cryptography and Security · Computer Science 2025-06-24 Zhengwu Huang , Ding Deng , Pengyue Sun , Guangfu Sun , Xiaomei Tang

The challenges associated with effectively programming FPGAs have been a major blocker in popularising reconfigurable architectures for HPC workloads. However new compiler technologies, such as MLIR, are providing new capabilities which…

Distributed, Parallel, and Cluster Computing · Computer Science 2023-10-04 Gabriel Rodriguez-Canal , Nick Brown , Maurice Jamieson , Emilien Bauer , Anton Lydike , Tobias Grosser

In the field of cryptography till date the 1-byte in 1-clock is the best known RC4 hardware design [1], while the 1-byte in 3clocks is the best known implementation [2,3]. The design algorithm in [1] considers two consecutive bytes together…

Hardware Architecture · Computer Science 2012-07-30 Rourab Paul , Sangeet Saha , Jkm Sadique Uz Zaman , Suman Das , Amlan Chakrabarti , Ranjan Ghosh

Division algorithms have been developed to reduce latency and to improve the efficiency of the processors. Floating point division is considered as a high latency operation. This papers looks into one such division algorithm, examines the…

Hardware Architecture · Computer Science 2019-09-24 Taposh Dutta Roy

Matrix Factorization (MF) has been widely applied in machine learning and data mining. A large number of algorithms have been studied to factorize matrices. Among them, stochastic gradient descent (SGD) is a commonly used method.…

Distributed, Parallel, and Cluster Computing · Computer Science 2020-06-30 Yuanhang Yu , Dong Wen , Ying Zhang , Xiaoyang Wang , Wenjie Zhang , Xuemin Lin

Traditional logic programming relies on symbolic computation on the CPU, which can limit performance for large-scale inference tasks. Recent advances in GPU hardware enable high-throughput matrix operations, motivating a shift toward…

Symbolic Computation · Computer Science 2025-08-20 Lun Ai

We analyze the bit complexity of efficient algorithms for fundamental optimization problems, such as linear regression, $p$-norm regression, and linear programming (LP). State-of-the-art algorithms are iterative, and in terms of the number…

Data Structures and Algorithms · Computer Science 2023-04-06 Mehrdad Ghadiri , Richard Peng , Santosh S. Vempala

The Baugh-Wooley algorithm is a well-known iterative algorithm for performing multiplication in digital signal processing applications. Decomposition logic is used with Baugh-Wooley algorithm to enhance the speed and to reduce the critical…

Hardware Architecture · Computer Science 2015-09-14 Ananda Kiran , Navdeep Prashar

The rapid advancements in artificial intelligence (AI), particularly the Large Language Models (LLMs), have profoundly affected our daily work and communication forms. However, it is still a challenge to deploy LLMs on resource-constrained…

Hardware Architecture · Computer Science 2025-03-03 Mingqiang Huang , Ao Shen , Kai Li , Haoxiang Peng , Boyu Li , Yupeng Su , Hao Yu

Matrix multiplications between asymmetric bit-width operands, especially between 8- and 4-bit operands are likely to become a fundamental kernel of many important workloads including neural networks and machine learning. While existing SIMD…

Machine Learning · Computer Science 2020-08-04 Dibakar Gope , Jesse Beu , Matthew Mattina

In this paper, we propose a mixed-precision convolution unit architecture which supports different integer and floating point (FP) precisions. The proposed architecture is based on low-bit inner product units and realizes higher precision…

Hardware Architecture · Computer Science 2021-01-29 Hamzah Abdel-Aziz , Ali Shafiee , Jong Hoon Shin , Ardavan Pedram , Joseph H. Hassoun

Solving the discrete logarithm problem in a finite prime field is an extremely important computing problem in modern cryptography. The hardness of solving the discrete logarithm problem in a finite prime field is the security foundation of…

Cryptography and Security · Computer Science 2026-05-28 Wen Huang

In this work, we present efficient modulation, a novel design for efficient vision networks. We revisit the modulation mechanism, which operates input through convolutional context modeling and feature projection layers, and fuses features…

Computer Vision and Pattern Recognition · Computer Science 2024-04-01 Xu Ma , Xiyang Dai , Jianwei Yang , Bin Xiao , Yinpeng Chen , Yun Fu , Lu Yuan

In the context of mapping high-level algorithms to hardware, we consider the basic problem of generating an efficient hardware implementation of a single threaded program, in particular, that of an inner loop. We describe a control-flow…

Hardware Architecture · Computer Science 2014-11-05 Madhav Desai

The work aims to improve the existing fast load shedding algorithm for industrial power system to increase performance, reliability, and scalability for future expansions. The paper illustrates the development of a scalable algorithm to…

Systems and Control · Electrical Eng. & Systems 2021-11-15 Andrea Petriccioli , Samuele Grillo , David Comunello , Andrea Cacace

Bloom filters are a fundamental data structure for approximate membership queries, with applications ranging from data analytics to databases and genomics. Several variants have been proposed to accommodate parallel architectures. GPUs,…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-12-18 Daniel Jünger , Kevin Kristensen , Yunsong Wang , Xiangyao Yu , Bertil Schmidt
‹ Prev 1 4 5 6 7 8 10 Next ›