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This work discusses memory-immersed collaborative digitization among compute-in-memory (CiM) arrays to minimize the area overheads of a conventional analog-to-digital converter (ADC) for deep learning inference. Thereby, using the proposed…

Hardware Architecture · Computer Science 2023-07-11 Shamma Nasrin , Maeesha Binte Hashem , Nastaran Darabi , Benjamin Parpillon , Farah Fahim , Wilfred Gomes , Amit Ranjan Trivedi

Dedicated accelerators are being designed to address the huge resource requirement of the deep neural network (DNN) applications. The power, performance and area (PPA) constraints limit the number of MACs available in these accelerators.…

Hardware Architecture · Computer Science 2021-02-25 Mahesh Chandra

To address memory and computation resource limitations for hardware-oriented acceleration of deep convolutional neural networks (CNNs), we present a computation flow, stacked filters stationary flow (SFS), and a corresponding data encoding…

Computer Vision and Pattern Recognition · Computer Science 2018-02-07 Yuechao Gao , Nianhong Liu , Sheng Zhang

Current ripple minimization is one of the challenges in parallel converters to increase the capacitor lifetime in various applications. In this paper, a deep neural network-based phase-shifting (PS) technique is proposed for…

Systems and Control · Electrical Eng. & Systems 2024-12-06 E. Karimi , S. Shahnooshi , E. Meshkati , T. Dragičević , F. Blaabjerg

Convolutional neural networks (CNNs) are one of the most successful machine learning techniques for image, voice and video processing. CNNs require large amounts of processing capacity and memory bandwidth. Hardware accelerators have been…

Hardware Architecture · Computer Science 2018-05-03 James Garland , David Gregg

Charge-domain compute-in-memory (CIM) SRAMs have recently become an enticing compromise between computing efficiency and accuracy to process sub-8b convolutional neural networks (CNNs) at the edge. Yet, they commonly make use of a fixed…

Hardware Architecture · Computer Science 2024-12-30 Adrian Kneip , Martin Lefebvre , Pol Maistriaux , David Bol

The state-of-art DNN structures involve intensive computation and high memory storage. To mitigate the challenges, the memristor crossbar array has emerged as an intrinsically suitable matrix computation and low-power acceleration framework…

Signal Processing · Electrical Eng. & Systems 2019-09-04 Xiaolong Ma , Geng Yuan , Sheng Lin , Caiwen Ding , Fuxun Yu , Tao Liu , Wujie Wen , Xiang Chen , Yanzhi Wang

DNNs are widely used but face significant computational costs due to matrix multiplications, especially from data movement between the memory and processing units. One promising approach is therefore Processing-in-Memory as it greatly…

Hardware Architecture · Computer Science 2024-01-19 Lorenzo Sonnino , Shaswot Shresthamali , Yuan He , Masaaki Kondo

Deep neural networks (DNNs) have revolutionized the field of artificial intelligence and have achieved unprecedented success in cognitive tasks such as image and speech recognition. Training of large DNNs, however, is computationally…

The inherent dynamics of the neuron membrane potential in Spiking Neural Networks (SNNs) allows processing of sequential learning tasks, avoiding the complexity of recurrent neural networks. The highly-sparse spike-based computations in…

Hardware Architecture · Computer Science 2021-07-09 Amogh Agrawal , Mustafa Ali , Minsuk Koo , Nitin Rathi , Akhilesh Jaiswal , Kaushik Roy

The acceleration of pruned Deep Neural Networks (DNNs) on edge devices such as Microcontrollers (MCUs) is a challenging task, given the tight area- and power-constraints of these devices. In this work, we propose a three-fold contribution…

Machine Learning · Computer Science 2025-03-20 Francesco Daghero , Daniele Jahier Pagliari , Francesco Conti , Luca Benini , Massimo Poncino , Alessio Burrello

Inference for Deep Neural Networks is increasingly being executed locally on mobile and embedded platforms due to its advantages in latency, privacy and connectivity. Since modern System on Chips typically execute a combination of different…

Computer Vision and Pattern Recognition · Computer Science 2021-05-11 Lei Xun , Long Tran-Thanh , Bashir M Al-Hashimi , Geoff V. Merrett

Recently, RRAM-based Binary Neural Network (BNN) hardware has been gaining interests as it requires 1-bit sense-amp only and eliminates the need for high-resolution ADC and DAC. However, RRAM-based BNN hardware still requires…

Neural and Evolutionary Computing · Computer Science 2019-04-16 Yulhwa Kim , Hyungjun Kim , Jae-Joon Kim

Convolutional neural networks (CNNs) play a key role in deep learning applications. However, the large storage overheads and the substantial computation cost of CNNs are problematic in hardware accelerators. Computing-in-memory (CIM)…

Hardware Architecture · Computer Science 2021-05-26 Syuan-Hao Sie , Jye-Luen Lee , Yi-Ren Chen , Chih-Cheng Lu , Chih-Cheng Hsieh , Meng-Fan Chang , Kea-Tiong Tang

The cost involved in training deep neural networks (DNNs) on von-Neumann architectures has motivated the development of novel solutions for efficient DNN training accelerators. We propose a hybrid in-memory computing (HIC) architecture for…

Hardware Architecture · Computer Science 2021-02-11 Vinay Joshi , Wangxin He , Jae-sun Seo , Bipin Rajendran

Recently, analog compute-in-memory (CIM) architectures based on emerging analog non-volatile memory (NVM) technologies have been explored for deep neural networks (DNN) to improve energy efficiency. Such architectures, however, leverage…

Signal Processing · Electrical Eng. & Systems 2020-08-07 Zhe Wan , Tianyi Wang , Yiming Zhou , Subramanian S. Iyer , Vwani P. Roychowdhury

Analog in-memory computing (AIMC) -- a promising approach for energy-efficient acceleration of deep learning workloads -- computes matrix-vector multiplications (MVMs) but only approximately, due to nonidealities that often are…

The accuracy of neural networks has greatly improved across various domains over the past years. Their ever-increasing complexity, however, leads to prohibitively high energy demands and latency in von Neumann systems. Several…

Hardware Architecture · Computer Science 2024-01-24 João Paulo C. de Lima , Asif Ali Khan , Luigi Carro , Jeronimo Castrillon

Binary neural networks (BNNs) that use 1-bit weights and activations have garnered interest as extreme quantization provides low power dissipation. By implementing BNNs as computing-in-memory (CIM), which computes multiplication and…

Machine Learning · Computer Science 2021-10-20 Minh-Son Le , Thi-Nhan Pham , Thanh-Dat Nguyen , Ik-Joon Chang

Optical computing has been recently proposed as a new compute paradigm to meet the demands of future AI/ML workloads in datacenters and supercomputers. However, proposed implementations so far suffer from lack of scalability, large…

Hardware Architecture · Computer Science 2022-10-21 Daniel Sturm , Sajjad Moazeni