Related papers: Preliminary Design of a General Electronics Platfo…
In preparation of the operation of the CMS electromagnetic calorimeter (ECAL) barrel at the High Luminosity Large Hadron Collider (HL-LHC) the entire on-detector electronics will be replaced. The new readout electronics comprises 12240 very…
The concept of dielectric-laser acceleration (DLA) provides the highest gradients among breakdown-limited (nonplasma) particle accelerators and thus the potential of miniaturization. The implementation of a fully scalable electron…
The first stage of the ATLAS Fast TracKer (FTK) is an ATCA-based input interface system, where hits from the entire silicon tracker are clustered and organized into overlapping eta-phi trigger towers before being sent to the tracking…
As the complexity of the scan algorithm is dependent on the number of design registers, large SoC scan designs can no longer be verified in RTL simulation unless partitioned into smaller sub-blocks. This paper proposes a methodology to…
High energy physics experiments in KEK/Japan rush into over KHz trigger stage. Thus, we need a successor of the data acquisition(DAQ) system that replaces the CAMAC or FASTBUS systems. To meet these needs, we have developed a DAQ system…
ATLAS LAr calorimeter will perform its Phase-I upgrade during the long shut down (LS2) in 2018, a new LAr Trigger Digitizer Board (LTDB) will be designed and installed. Several commercial-off-the-shelf (COTS) multichannel high-speed ADCs…
The concept of Dielectric Laser Acceleration (DLA) provides highest gradients among non-plasma particle accelerators. However, stable beam transport and staging have not been shown experimentally yet. We present a scheme that confines the…
This paper presents our approach for making FPGA accelerators accessible to software (SW) programmers. It is intended as a starting point for collaborations with other groups pursuing similar objectives. We report on our current SAccO…
The upgrade of the ALICE TPC will allow the experiment to cope with the high interaction rates foreseen for the forthcoming Run 3 and Run 4 at the CERN LHC. In this article, we describe the design of new readout chambers and front-end…
Compared to conventional general-purpose processors, accelerator-rich architectures (ARAs) can provide orders-of-magnitude performance and energy gains and are emerging as one of the most promising solutions in the age of dark silicon.…
Multi-Access or Mobile Edge Computing (MEC) is being deployed by 4G/5G operators to provide computational services at lower latencies. Federating MECs across operators expands capability, capacity, and coverage but gives rise to two issues…
We describe a modular multi-channel data acquisition system based on the 5-15 Gigasample-per-second waveform-recording PSEC4 chip. The system architecture incorporates two levels of hardware with FPGA-embedded system control and in-line…
Electronic systems are becoming more and more ubiquitous as our world digitises. Simultaneously, even basic components are experiencing a wave of improvements with new transistors, memristors, voltage/current references, data converters,…
Accelerometers have widespread applications and are an essential component in many areas such as automotive, consumer electronics and industrial applications. Most commercial accelerometers are based on micro-electromechanical system (MEMS)…
Operations typically used in machine learning al-gorithms (e.g. adds and soft max) can be implemented bycompact analog circuits. Analog Application-Specific Integrated Circuit (ASIC) designs that implement these algorithms using techniques…
A dedicated front-end electronics has been developed for the trigger chambers of the ALICE muon spectrometer which will work at the future LHC at CERN. These trigger chambers are based on RPCs (Resistive Plate Chambers) working in streamer…
Computing platforms in autonomous vehicles record large amounts of data from many sensors, process the data through machine learning models, and make decisions to ensure the vehicle's safe operation. Fast, accurate, and reliable…
This paper describes two research projects that develop new low-cost techniques for testing devices with multiple high-speed (2 to 5 Gbps) signals. Each project uses commercially available components to keep costs low, yet achieves…
Designing field-programmable gate array (FPGA)-based accelerators for modern artificial intelligence workloads requires navigating a large and complex hardware design space encompassing architectural parameters, dataflow strategies, and…
The increase in open-source availability of Large Language Models (LLMs) has enabled users to deploy them on more and more resource-constrained edge devices to reduce reliance on network connections and provide more privacy. However, the…