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An essential component for the Fifth Generation of Mobile Networks deployments is the 5G Core (5GC), which bridges the 5G Radio Access Network (RAN) to the rest of the Internet. Some open-source platforms for the 5GC have emerged and been…

Networking and Internet Architecture · Computer Science 2024-12-31 Maria Barbosa , Marcelo Silva , Ednelson Cavalcanti , Kelvin Dias

The current workloads and applications are highly diversified, facing critical challenges such as the Power Wall and the Memory Wall Problem. Different strategies over the multiple levels of Caches have evolved to mitigate these problems.…

Hardware Architecture · Computer Science 2023-04-13 Murali Dadi , Shubhang Pandey , Aparna Behera , T G Venkatesh

The deployment of large-scale software-based 5G core functions presents significant challenges due to their reliance on optimized and intelligent resource provisioning for their services. Many studies have focused on analyzing the impact of…

Cryptography and Security · Computer Science 2025-07-25 Rodrigo Moreira , Larissa F. Rodrigues Moreira , Flávio de Oliveira Silva

The 5th-generation wireless networks (5G) technologies and mobile edge computing (MEC) provide great promises of enabling new capabilities for the industrial Internet of Things. However, the solutions enabled by the 5G ultra-reliable…

Networking and Internet Architecture · Computer Science 2022-02-16 Peng Hu , Jinhuan Zhang

As capacity and complexity of on-chip cache memory hierarchy increases, the service cost to the critical loads from Last Level Cache (LLC), which are frequently repeated, has become a major concern. The processor may stall for a…

Hardware Architecture · Computer Science 2016-08-09 Navid Khoshavi , Xunchao Chen , Jun Wang , Ronald F. DeMara

An effective way to improve energy efficiency is to throttle hardware resources to meet a certain performance target, specified as a QoS constraint, associated with all applications running on a multicore system. Prior art has proposed…

Hardware Architecture · Computer Science 2019-11-14 Mehrzad Nejat , Madhavan Manivannan , Miquel Pericas , Per Stenstrom

High load latency that results from deep cache hierarchies and relatively slow main memory is an important limiter of single-thread performance. Data prefetch helps reduce this latency by fetching data up the hierarchy before it is…

Hardware Architecture · Computer Science 2021-03-30 Majid Jalili , Mattan Erez

As 5G networks strive to support advanced time-critical applications, such as immersive Extended Reality (XR), cloud gaming, and autonomous driving, the demand for Real-time Broadband Communication (RTBC) grows. In this article, we present…

Networking and Internet Architecture · Computer Science 2024-10-23 Guangjin Pan , Shugong Xu , Pin Jiang

Ultra-reliable low-latency vehicular communications (URLLC) require sufficient physical-layer (PHY) compute headroom at the network edge, where roadside units (RSUs) and compact next-generation base stations (gNBs) must meet strict timing…

Distributed, Parallel, and Cluster Computing · Computer Science 2026-03-10 Ryan Barker , Julia Boone , Tolunay Seyfi , Alireza Ebrahimi Dorcheh , Fatemeh Afghah , Joseph Boccuzzi

Traditional on-die, three-level cache hierarchy design is very commonly used but is also prone to latency, especially at the Level 2 (L2) cache. We discuss three distinct ways of improving this design in order to have better performance.…

Hardware Architecture · Computer Science 2021-01-26 Pranjal Singh Rajput , Sonnya Dellarosa , Kanya Satis

The fifth-generation cellular mobile networks are expected to support mission critical ultra-reliable low latency communication (URLLC) services in addition to the enhanced mobile broadband applications. This article first introduces three…

Information Theory · Computer Science 2018-08-09 He Chen , Rana Abbas , Peng Cheng , Mahyar Shirvanimoghaddam , Wibowo Hardjawana , Wei Bao , Yonghui Li , Branka Vucetic

Parallel programming is emerging fast and intensive applications need more resources, so there is a huge demand for on-chip multiprocessors. Accessing L1 caches beside the cores are the fastest after registers but the size of private caches…

Performance · Computer Science 2016-09-27 Diman Zad Tootaghaj , Farshid Farhat

Cache plays a critical role in reducing the performance gap between CPU and main memory. A modern multi-core CPU generally employs a multi-level hierarchy of caches, through which the most recently and frequently used data are maintained in…

Hardware Architecture · Computer Science 2021-06-01 Rui Wang , Chundong Wang , Chongnan Ye

Vehicle automation is driving the integration of advanced sensors and new applications that demand high-quality information, such as collaborative sensing for enhanced situational awareness. In this work, we considered a vehicular sensing…

Networking and Internet Architecture · Computer Science 2024-04-01 Pablo Fondo-Ferreiro , David Candal-Ventureira , Francisco Javier González-Castaño , Felipe Gil-Castiñeira

One of the paramount advantages of multi-level cache-enabled (MLCE) networks is pushing contents proximity to the network edge and proactively caching them at multiple transmitters (i.e., small base-stations (SBSs), unmanned aerial vehicles…

Information Theory · Computer Science 2021-02-09 Mohammed S. Al-Abiad , Md. Zoheb Hassan , Md. Jahangir Hossain

The performances of the fifth generation (5G) wireless communication systems are significantly affected by edge cache and transport network. These emerging components bring substantial costs of the placement and utilization, and the…

Information Theory · Computer Science 2016-10-05 Zhipeng Yan , Mugen Peng , Chonggang Wang

The development of 5G networks has enabled support for a vast number of applications with stringent traffic requirements, both in terms of communication and computation. Furthermore, the proximity of the entities, such as edge servers and…

Networking and Internet Architecture · Computer Science 2024-07-11 Endri Goshi , Hasanin Harkous , Shohreh Ahvar , Rastin Pries , Fidan Mehmeti , Wolfgang Kellerer

With technology scaling, the size of cache systems in chip-multiprocessors (CMPs) has been dramatically increased to efficiently store and manipulate a large amount of data in future applications and decrease the gap between cores and…

Hardware Architecture · Computer Science 2022-01-04 Pooneh Safayenikoo , Arghavan Asad , Mahmood Fathy

The surge of mobile data traffic forces network operators to cope with capacity shortage. The deployment of small cells in 5G networks is meant to reduce latency, backhaul traffic and increase radio access capacity. In this context, mobile…

Computer Science and Game Theory · Computer Science 2016-12-07 Francesco De Pellegrini , Antonio Massaro , Leonardo Goratti , Rachid El-Azouzi

Decentralized coded content caching for next generation cellular networks is studied. The contents are linearly combined and cached in under-utilized caches of User Terminals (UTs) and its throughput capacity is compared with decentralized…

Information Theory · Computer Science 2016-11-10 Mohsen Karimzadeh Kiskani , Hamid R. Sadjadpour