Related papers: Preliminary Design of Scalable Hardware Integrated…

The new electronics of the ATLAS Tile Calorimeter for the HL-LHC interfaces the on-detector and off-detector electronics by means of a Daughterboard. The Daughterboard is positioned on-detector featuring commercial SFPs+, CERN GBTx ASICs,…

We propose a new fixed latency scheme for Xilinx gigabit transceivers that will be used in the upgrade of the ATLAS forward muon spectrometer at the Large Hadron Collider. The fixed latency scheme is implemented in a 4.8 Gbps link between a…

A scalable readout system (SRS) is designed to provide a general solution for different micro-pattern gas detectors. The system mainly consists of three kinds of modules: the ASIC card, the Adapter card and the Front-End Card (FEC). The…

This paper presents significant frequency scaling of acoustic filter technology to 50 GHz. This achievement is enabled by the P3F LiNbO3 multilayer stack, in which piezoelectric thin-films of alternating orientations are transferred in…

In this paper, we demonstrate the integration of photonic devices on sapphire substrates using multi-layer depressed cladding waveguides at both 780 nm and 1550 nm. The devices are up to 10-cm long and written at depths down to 400 um. The…

The Front End Driver, FED, is a 9U 400mm VME64x card designed for reading out the Compact Muon Solenoid, CMS, silicon tracker signals transmitted by the APV25 analogue pipeline Application Specific Integrated Circuits. The FED receives the…

This work describes the LLRF and control system in use for a novel accelerator structure developed for a compact design operating in C-band developed by SLAC, with collaboration from RadiaBeam and RadiaSoft. This design is a pulsed…

We demonstrate a novel architecture for Adaptive Optics (AO) control based on FPGAs (Field Programmable Gate Arrays), making active use of their configurable parallel processing capability. SPARC's unique capabilities are demonstrated…

A new generation of radio telescopes is achieving unprecedented levels of sensitivity and resolution, as well as increased agility and field-of-view, by employing high-performance digital signal processing hardware to phase and correlate…

We introduce an open-source architecture for next-generation Radio-Access Network baseband processing: 1024 latency-tolerant 32-bit RISC-V cores share 4 MiB of L1 memory via an ultra-low latency interconnect (7-11 cycles), a modular Direct…

Large port count spatial optical switches will facilitate flexible and energy efficient data movement in future data communications systems, especially if they are capable of nanosecond-order reconfiguration times. In this work, we…

Software defined radio (SDR) allows unprecedented levels of flexibility by transitioning the radio communication system from a rigid hardware platform to a more user-controlled software paradigm. However, it can still be time consuming to…

We propose without loss of generality strategies to achieve a high-throughput FPGA-based architecture for a QC-LDPC code based on a circulant-1 identity matrix construction. We present a novel representation of the parity-check matrix (PCM)…

Achieving high performance, energy efficiency, and cost-effectiveness while maintaining architectural flexibility is a critical challenge in the development and deployment of edge AI devices. Monolithic SoC designs struggle with this…

A prototype optical-link board has been developed for the ATLAS Liquid Argon Calorimeter Phase-2 upgrade. The board consists of 24 lpGBT chips and 8 VTRx+ modules and demonstrates the full optical link design of the future front-end board.…

This work describes the architecture of a digital LLRF system for heavy-ion acceleration developed under the specification of the projected future heavy-ion accelerator facility in Huelva, Spain. A prototype LLRF test bench operating at…

High Bandwidth Memory (HBM) provides massive aggregated memory bandwidth by exposing multiple memory channels to the processing units. To achieve high performance, an accelerator built on top of an FPGA configured with HBM (i.e., FPGA-HBM…

Caribou is a versatile data acquisition (DAQ) system developed within several collaborative frameworks (CERN EP R&D, DRD3, AIDAinnova, and Tangerine) to support laboratory and test-beam characterization of novel silicon pixel detectors. It…

The VMM3a is an Application Specific Integrated Circuit (ASIC), specifically developed for the readout of gaseous detectors. Originally developed within the ATLAS New Small Wheel (NSW) upgrade, it has been successfully integrated into the…

The increasing demand for on-device intelligence in Edge AI and TinyML applications requires the efficient execution of modern Convolutional Neural Networks (CNNs). While lightweight architectures like MobileNetV2 employ Depthwise Separable…