Related papers: Preliminary Design of Scalable Hardware Integrated…

The demand for energy-efficient and high performance embedded systems drives the evolution of new hardware architectures, including concepts like approximate computing. This paper presents a novel reconfigurable embedded platform named…

Transverse Deflecting Cavities (TDCs) are generally adopted for electron beam diagnosis. Three sets of S-band and two sets of X-band TDCs are planned at Shenzhen Superconducting Soft X-ray Free Electron Laser (S3FEL) to accurately measure…

The recent submission of Google TPU-v3 Pods to the industry wide MLPerf v0.6 training benchmark demonstrates the scalability of a suite of industry relevant ML models. MLPerf defines a suite of models, datasets and rules to follow when…

ATLAS LAr calorimeter will perform its Phase-I upgrade during the long shut down (LS2) in 2018, a new LAr Trigger Digitizer Board (LTDB) will be designed and installed. Several commercial-off-the-shelf (COTS) multichannel high-speed ADCs…

A compact low-level RF (LLRF) control system based on RF system-on-chip (RFSoC) technology has been designed for the Advanced Concept Compact Electron Linear-accelerator (ACCEL) program, which has challenging requirements in both RF…

Emerging Internet-of-Things sensing applications rely on ultra low-power (ULP) microcontroller units (MCUs) that wirelessly transmit data to the cloud. Typical MCUs nowadays consist of generic blocks, except for the protocol-specific radios…

We present a control and measurement setup for superconducting qubits based on Xilinx 16-channel radio-frequency system-on-chip (RFSoC) device. The proposed setup consists of four parts: multiple RFSoC boards, a setup to synchronise every…

The Phase-2 ATLAS upgrade for the High Luminosity Large Hadron Collider (HL-LHC) has motivated progressive redesigns of the ATLAS Tile Calorimeter (TileCal) read-out link and control board (Daughterboard). The Daughterboard (DB)…

Hardware acceleration has emerged as a key research topic for supporting computationally intensive signal processing and artificial intelligence applications in 6G research and development studies. This paper presents an RF Network on Chip…

The rapid advancement of energy-efficient parallel ultra-low-power (ULP) ucontrollers units (MCUs) is enabling the development of autonomous nano-sized unmanned aerial vehicles (nano-UAVs). These sub-10cm drones represent the next…

We present and evaluate the ExaNeSt Prototype, a liquid-cooled rack prototype consisting of 256 Xilinx ZU9EG MPSoCs, 4 TBytes of DRAM, 16 TBytes of SSD, and configurable interconnection 10-Gbps hardware. We developed this testbed in…

Building upon existing signal processing techniques and open-source software, this paper presents a baseline design for an RF System-on-Chip Frequency Division Multiplexed readout for a spatio-spectral focal plane instrument based on low…

The GANDALF 6U-VME64x/VXS module has been designed to cope with a variety of readout tasks in high energy and nuclear physics experiments, in particular the COMPASS experiment at CERN. The exchangeable mezzanine cards allow for an…

RC4 can be made more secured if an additional RC4-like Post-KSA Random Shuffing (PKRS) process is introduced between KSA and PRGA. It can also be made significantly faster if RC4 bytes are processed in a FPGA embedded system using multiple…

The PSEC4 custom integrated circuit was designed for the recording of fast waveforms for use in large-area time-of-flight detector systems. The ASIC has been fabricated using the IBM-8RF 0.13 micron CMOS process. On each of 6 analog…

We have developed a quantum annealing processor, based on an array of tunably coupled rf-SQUID flux qubits, fabricated in a superconducting integrated circuit process [1]. Implementing this type of processor at a scale of 512 qubits and…

The extremely high computational and storage demands of large language models have excluded most edge devices, which were widely used for efficient machine learning, from being viable options. A typical edge device usually only has 4GB of…

In this paper we describe a single-node, double precision Field Programmable Gate Array (FPGA) implementation of the Conjugate Gradient algorithm in the context of Lattice Quantum Chromodynamics. As a benchmark of our proposal we invert…

This paper reports an implementation of the PHY specifications of the IEEE 802.15.4 standard for the frequency band 868 915 MHz on a Software Defined Radio (SDR) platform. This standard is defined for low power, low data rate and low cost…

The functions of the Low-Level Radio Frequency (LLRF) system at European Spallation Source (ESS) are implemented on different Field-Programmable Gate Array (FPGA) boards in a Micro Telecommunications Computing Architecture (MTCA) crate.…