Related papers: Digital LLRF system for TRIUMF ISIS buncher

Normal conducting linear particle accelerators consist of multiple rf stations with accelerating structure cavities. Low-level rf (LLRF) systems are employed to set the phase and amplitude of the field in the accelerating structure, and to…

This paper presents a low power, low jitter LC phase locked loop (PLL) which has been designed and fabricated in a commercial 0.25-um Silicon-on-Sapphire CMOS technology. Random jitter and deterministic jitter of the PLL are 1.3 ps and 7.5…

A new bunching method, named "kladistron" has been developed at CEA in order to provide high efficiency klystrons. A first "kladistron" prototype was designed and realized. It was adapted from the 4.9 GHz TH2166 from Thales, where the…

Low Level RF (LLRF) control systems of linear accelerators (LINACs) are typically implemented with heterodyne based architectures, which have complex analog RF mixers for up and down conversion. The Gen 3 Radio Frequency System-on-Chip…

The main physics programme of the International Linear Collider (ILC) requires a measurement of the beam energy at the interaction point with an accuracy of $10^{-4}$ or better. To achieve this goal a magnetic spectrometer using high…

We describe the newest generation of the SLAC Microresonator RF (SMuRF) electronics, a warm digital control and readout system for microwave-frequency resonator-based cryogenic detector and multiplexer systems such as microwave SQUID…

The LCLS began operations in 2009, utilizing SLAC's normal-conducting (NC) LINAC, which features control equipment dating back to the 1960s and 1980s. The Linac Electronics Modernization Plan (LEMP) aims to replace the legacy control…

The Fermilab Booster uses multi-turn beam injection with all its cavities phased such that beam sees a net zero RF voltage even when each station is at the same maxi-mum voltage. During beam capture the RF voltage is increased slowly by…

The Advanced Light Source (ALS) at LBNL is upgrading several LLRF systems for its Linac and Sub-Harmonic Bunchers, where it is desired to have a unified LLRF system design to support various RF frequencies (at 125MHz, 500MHz and 3GHz) and…

We present a description of the Radio Frequency Quadrupole (RFQ) ion trap built as part of the TITAN facility. It consists of a gas-filled, segmented, linear Paul trap and is the first stage of the TITAN setup with the purpose of cooling…

Shanghai Synchrotron Radiation Facility (SSRF), is one of the third-generation high-beam current (3.5 GeV) synchrotron light sources. In the storage ring of SSRF, multi-bunch instabilities would increase beam emittance and energy spread,…

In order to double the positron injection rate into the KEKB ring, a two-bunch acceleration scheme has been studied at the linac, in which bunches separated by 96 ns are accelerated in 50 Hz. In this scheme the stabilization of energy and…

Superconducting cavities (SRF) are widely used in new generation particle accelerators, increasing the requirements and specifications for new designs. The LLRF control system, including the detuning control due to mechanical perturbations,…

The off-frequency detune method is being considered for application in the LCLS-II-HE superconducting linac to produce multi-energy electron beams for supporting multiple undulator lines simultaneously [1]. Design of the tuner has been…

In the framework of the "LHC Injectors Upgrade" (LIU) project, the CERN Proton Synchrotron (PS) is being prepared as a pre-injector for the Large Hadron Collider at high luminosity (HL-LHC). RF systems at 20 MHz, 40 MHz and 80 MHz are…

The J-PARC linac was consist of 324MHz low-{\beta} section and 972MHz high-{\beta} section. There is a total of 48 stations. And each station was equipped with an independent LLRF (Low-Level Radio Frequency) system to realize an…

The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators.…

This paper presents the design and simulation results of a gigabit transceiver Application Specific Integrated Circuit (ASIC) called GBCR for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR has four upstream receiver…

ISIS (In-situ Storage Imaging Sensor) is a novel CMOS sensor with multiple charge storage capability developed for the ILC vertex detector by the Linear Collider Flavour Identification (LCFI) collaboration. This paper reports test results…

We have developed a prototype system for the ILC vertex detector based on DEPFET pixels. The system operates a 128x64 matrix (with ~35x25 square micron large pixels) and uses two dedicated microchips, the SWITCHER II chip for matrix…