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Aggregated HPC resources have rigid allocation systems and programming models which struggle to adapt to diverse and changing workloads. Consequently, HPC systems fail to efficiently use the large pools of unused memory and increase the…

Distributed, Parallel, and Cluster Computing · Computer Science 2024-07-29 Marcin Copik , Marcin Chrapek , Larissa Schmid , Alexandru Calotoiu , Torsten Hoefler

Many HPC applications suffer from a bottleneck in the shared caches, instruction execution units, I/O or memory bandwidth, even though the remaining resources may be underutilized. It is hard for developers and runtime systems to ensure…

Distributed, Parallel, and Cluster Computing · Computer Science 2021-03-17 Felippe V. Zacarias , Vinicius Petrucci , Rajiv Nishtala , Paul Carpenter , Daniel Mossé

Conventional cache models are not suited for real-time parallel processing because tasks may flush each other's data out of the cache in an unpredictable manner. In this way the system is not compositional so the overall performance is…

Hardware Architecture · Computer Science 2011-11-09 A. M. Molnos , M. J. M. Heijligers , S. D. Cotofana , J. T. J. Van Eijndhoven

Compute in-memory (CIM) is a promising technique that minimizes data transport, the primary performance bottleneck and energy cost of most data intensive applications. This has found wide-spread adoption in accelerating neural networks for…

Hardware Architecture · Computer Science 2020-08-18 Brian Crafton , Samuel Spetalnick , Gauthaman Murali , Tushar Krishna , Sung-Kyu Lim , Arijit Raychowdhury

Emerging applications, such as big data analytics and machine learning, require increasingly large amounts of main memory, often exceeding the capacity of current commodity processors built on DRAM technology. To address this, recent…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-10-27 Manel Lurbe , Miguel Avargues , Salvador Petit , Maria E. Gomez , Rui Yang , Guanhao Wang , Julio Sahuquillo

Resource disaggregation offers a cost effective solution to resource scaling, utilization, and failure-handling in data centers by physically separating hardware devices in a server. Servers are architected as pools of processor, memory,…

Hardware Architecture · Computer Science 2023-01-25 Christina Giannoula , Kailong Huang , Jonathan Tang , Nectarios Koziris , Georgios Goumas , Zeshan Chishti , Nandita Vijaykumar

This extended report presents DDS, a novel disaggregated storage architecture enabled by emerging networking hardware, namely DPUs (Data Processing Units). DPUs can optimize the latency and CPU consumption of disaggregated storage servers.…

Distributed, Parallel, and Cluster Computing · Computer Science 2024-08-29 Qizhen Zhang , Philip Bernstein , Badrish Chandramouli , Jiasheng Hu , Yiming Zheng

Non-volatile, byte addressable, memory technology with performance close to main memory promises to revolutionise computing systems in the near future. Such memory technology provides the potential for extremely large memory regions (i.e. >…

Distributed, Parallel, and Cluster Computing · Computer Science 2018-05-28 Adrian Jackson , Michele Weiland , Mark Parsons , Bernhard Homoelle

FPGA-based data processing in datacenters is increasing in popularity due to the demands of modern workloads and the ensuing necessity for specialization in hardware. Driven by this trend, vendors are rapidly adapting reconfigurable devices…

Distributed, Parallel, and Cluster Computing · Computer Science 2020-04-06 Kaan Kara , Christoph Hagleitner , Dionysios Diamantopoulos , Dimitris Syrivelis , Gustavo Alonso

Disaggregating memory from compute offers the opportunity to better utilize stranded memory in cloud data centers. It is important to cache data in the compute nodes and maintain cache coherence across multiple compute nodes. However, the…

Databases · Computer Science 2026-01-14 Ruihong Wang , Jianguo Wang , Walid G. Aref

Contemporary memory systems contain a variety of memory types, each possessing distinct characteristics. This trend empowers applications to opt for memory types aligning with developer's desired behavior. As a result, developers gain…

Performance · Computer Science 2024-08-14 Andrès Rubio Proaño , Kento Sato

Nowadays, datacenters lean on a computer-centric approach based on monolithic servers which include all necessary hardware resources (mainly CPU, RAM, network and disks) to run applications. Such an architecture comes with two main…

Distributed, Parallel, and Cluster Computing · Computer Science 2021-04-12 Brice Ekane , Yohan Pipereau , Boris Teabe , Alain Tchana , Gael Thomas , Noel de palma , Daniel Hagimont

Multi-core architectures feature an intricate hierarchy of cache memories, with multiple levels and sizes. To adequately decompose an application according to the traits of a particular memory hierarchy is a cumbersome task that may be…

Distributed, Parallel, and Cluster Computing · Computer Science 2015-11-20 Hervé Paulino , Nuno Delgado

Although High Performance Computing (HPC) users understand basic resource requirements such as the number of CPUs and memory limits, internal infrastructural utilization data is exclusively leveraged by cluster operators, who use it to…

Distributed, Parallel, and Cluster Computing · Computer Science 2024-01-19 Abel Souza , Kristiaan Pelckmans , Johan Tordsson

Response time requirements for big data processing systems are shrinking. To meet this strict response time requirement, many big data systems store all or most of their data in main memory to reduce the access latency. Main memory…

Hardware Architecture · Computer Science 2016-08-29 Jason Lowe-Power , Mark D. Hill , David A. Wood

Collocating deep learning training tasks improves GPU utilization but risks resource contention, severe slowdowns, and out-of-memory (OOM) failures. Accurate memory estimation is essential for robust collocation, and GPU utilization…

Distributed, Parallel, and Cluster Computing · Computer Science 2026-04-29 Ehsan Yousefzadeh-Asl-Miandoab , Reza Karimzadeh , Danyal Yorulmaz , Bulat Ibragimov , Pınar Tözün

In this paper, we proposed an effective and efficient multi-core shared-cache design optimization approach based on reuse-distance analysis of the data traces of target applications. Since data traces are independent of system hardware…

Performance · Computer Science 2021-09-13 Hsin-Yu Ho , Ren-Song Tsay

Byte-addressable persistent memories (PM) has finally made their way into production. An important and pressing problem that follows is how to deploy them in existing datacenters. One viable approach is to attach PM as self-contained…

Distributed, Parallel, and Cluster Computing · Computer Science 2019-01-08 Shin-Yeh Tsai , Yiying Zhang

Large-scale AI training and inference require hundreds of gigabytes to terabytes of DRAM with high peak to average utilization ratios, resulting in overprovisioning. In cloud computing, DRAM constitutes a significant share of the cost. Yet,…

Hardware Architecture · Computer Science 2026-05-28 Kaustav Goswami , Maryam Babaie , Hoa Nguyen , Venkatesh Akella , Jason Lowe-Power

Gradient aggregation has long been identified as a major bottleneck in today's large-scale distributed machine learning training systems. One promising solution to mitigate such bottlenecks is gradient compression, directly reducing…

Machine Learning · Computer Science 2024-10-30 Wenchen Han , Shay Vargaftik , Michael Mitzenmacher , Brad Karp , Ran Ben Basat