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This manuscript describes a radiation-hardened current-mode delta-sigma ADC fabricated in a standard 130 nm CMOS technology and qualified for total ionizing doses up to 100 Mrad. The operational signal range achieved with a 100 s…
The present article introduces a novel ASIC architecture, designed in the context of the ATLAS Tile Calorimeter upgrade program for the High-Luminosity phase of the Large Hadron Collider at CERN. The architecture is based on…
We present the design and characterization of a large-area Cryogenic PhotoDetector (CPD) designed for active particle identification in rare event searches, such as neutrinoless double beta decay and dark matter experiments. The detector…
The proposed delta-sigma modulator ($\Delta\Sigma$M) based signal acquisition architecture uses a differential difference amplifier (DDA) customized for dual purpose roles, namely as instrumentation amplifier and as integrator of…
A wide swing charge sensitive amplifier (CSA) has been developed, as a part of a front-end electronics (FEE) readout ASIC, for a prototype silicon tungsten (Si-W) based electromagnetic (EM) calorimeter. The CSA, designed in 0.35 $\mu$m…
We developed a simple, flexible, low-cost, and computer-controlled cryogenic temperature measurement system for undergraduate instructional laboratories. An Arduino microcontroller board measures the voltage across a silicon diode to…
The water Cherenkov detector array (WCDA) is one of the key detectors in the large high altitude air shower observatory (LHAASO), which is proposed for very high gamma ray source survey. In WCDA, there are more than 3000 photomultiplier…
The radiation hardness of passive CMOS pixel sensors fabricated in 150 nm LFoundry technology is investigated. CMOS process lines are especially of interest for large-scale silicon detectors as they offer high production throughput at…
1 ps timing resolution is the entry point to signature based searches relying on secondary/tertiary vertices and particle identification. We describe a preliminary design for PSEC5, an 8-channel 40 GS/s waveform-sampling ASIC in the TSMC 65…
IDeF-X HD is a 32-channel analog front-end with self-triggering capability optimized for the readout of 16 x 16 pixels CdTe or CdZnTe pixelated detectors to build low power micro gamma camera. IDeF-X HD has been designed in the standard AMS…
An array of DEPFET pixels is one of several concepts to implement an active pixel sensor. Similar to PNCCD and SDD detectors, the typically 0.45 mm thick silicon sensor is fully depleted by the principle of sideward depletion. They have…
We report on a large active area (15x15mm2), high channel density (470 pixels/mm2), self-triggering CMOS analog chip that we have developed as pixelized charge collecting electrode of a Micropattern Gas Detector. This device, which…
Cooling high-power electronics in multilayer integrated circuits (ICs) is challenging for existing cooling methods. In this work, we designed through-chip microchannels (TCMCs) that cross the entire chip perpendicularly to the layers, with…
A full-wafer, 10,580 $\times$ 10,560 pixel (95 $\times$ 95 mm) CCD was designed and tested at Semiconductor Technology Associates (STA) with 9 um square pixels and 16 outputs. The chip was successfully fabricated in 2006 at DALSA and some…
The Large High Altitude Air Shower Observatory (LHAASO) is designed for high energy gamma ray and cosmic ray detection. A Water Cherenkov Detector Array which is sensitive to gamma ray showers above a few hundred GeV is proposed to survey…
We have designed and characterized a micro-SQUID with dispersive readout for use in low temperature scanning probe microscopy systems. The design features a capacitively shunted RF SQUID with a tunable resonance frequency from 5 to 12 GHz,…
A new TDC-chip is under development for the COMPASS experiment at CERN. The ASIC, which exploits the 0.6 micrometer CMOS sea-of-gate technology, will allow high resolution time measurements with digitization of 75 ps, and an unprecedented…
This study unveils a comprehensive design strategy, intricately addressing the realization of transmon qubits, the design of Josephson parametric amplifiers, and the development of an innovative fully integrated receiver dedicated to…
A monolithic silicon pixel prototype produced for the MONOLITH ERC Advanced project was irradiated with 70 MeV protons up to a fluence of 1 x 10^16 1 MeV n_eq/cm^2. The ASIC contains a matrix of hexagonal pixels with 100 {\mu}m pitch,…
We present the architecture, design and first test results of SPIDER, the first prototype of a TSMC CMOS 65 nm ASIC designed for the time measurement path of LHCb Electromagnetic Calorimeter after LS4 Upgrade. The main requirements for the…