Related papers: Inplace Access to the Surface Code Y Basis
Product codes (PCs) protect a two-dimensional array of bits using short component codes. Assuming transmission over the binary symmetric channel, the decoding is commonly performed by iteratively applying bounded-distance decoding to the…
We give a broad generalisation of the mapping, originally due to Dennis, Kitaev, Landahl and Preskill, from quantum error correcting codes to statistical mechanical models. We show how the mapping can be extended to arbitrary stabiliser or…
As quantum computers scale toward millions of physical qubits, it becomes essential to robustly encode individual logical qubits to ensure fault tolerance under realistic noise. A high-quality foundational encoding allows future compilation…
Topological quantum codes, such as toric and surface codes, are excellent candidates for hardware implementation due to their robustness against errors and their local interactions between qubits. However, decoding these codes efficiently…
Leveraging noise bias, where phase-flip errors dominate over bit-flips, can drastically reduce the hardware overhead of fault-tolerant quantum computation, but existing approaches require bias-preserving CNOT gates whose implementation…
Topological codes have many desirable properties that allow fault-tolerant quantum computation with relatively low overhead. A core challenge for these codes, however, is to achieve a low-overhead universal gate set with limited…
Logical qubits can be protected against environmental noise by encoding them into a highly entangled state of many physical qubits and actively intervening in the dynamics with stabilizer measurements. In this work, we numerically optimize…
It is well understood that a two-dimensional grid of locally-interacting qubits is a promising platform for achieving fault tolerant quantum computing. However in the near-future, it may prove less challenging to develop lower dimensional…
Decoders that provide an estimate of the probability of a logical failure conditioned on the error syndrome ("soft-output decoders") can reduce the overhead cost of fault-tolerant quantum memory and computation. In this work, we construct…
In fault-tolerant quantum computation, the preparation of logical states is a ubiquitous subroutine, yet significant challenges persist even for the simplest states required. In the present work, we present a unitary, scalable,…
Practical applications of quantum computing depend on fault-tolerant devices with error correction. Today, the most promising approach is a class of error-correcting codes called surface codes. We study the problem of compiling quantum…
In this paper, we explore the relationship between the width of a qubit lattice constrained in one dimension and physical thresholds for scalable, fault-tolerant quantum computation. To circumvent the traditionally low thresholds of small…
Qubit shuttling promises to advance some quantum computing platforms to the qubit register sizes needed for effective quantum error correction (QEC), but also introduces additional errors whose impact must be evaluated. The established…
We study the fidelity of the surface code in the presence of correlated errors induced by the coupling of physical qubits to a bosonic environment. By mapping the time evolution of the system after one quantum error correction cycle onto a…
Topological subsystem codes can combine the advantages of both topological codes and subsystem codes. Suchara et al. proposed a framework based on hypergraphs for construction of such codes. They also studied the performance of some…
We estimate the resource requirements for the quantum simulation of the ground state energy of the one dimensional quantum transverse Ising model (TIM), based on the surface code implementation of a fault tolerant quantum computer. The…
Spin qubits in semiconductor structures bring the promise of large-scale 2D integration, with the possibility to incorporate the control electronics on the same chip. In order to perform error correction on this platform, the characteristic…
We present a fault-tolerant mapping of rotated surface codes onto a $2\times N$ silicon spin-qubit railway architecture, utilizing electron shuttling to resolve the wiring fan-out bottleneck. Employing circuit-level noise modeling, we…
In Ref. [1], Bravyi et al. found examples of Bivariate Bicycle (BB) codes with similar logical performance to the surface code but with an improved encoding rate. In this work, we generalize a novel parity-check circuit design principle…
The surface code is a two-dimensional topological code with code parameters that scale optimally with the number of physical qubits, under the constraint of two-dimensional locality. In three spatial dimensions an analogous simple yet…