Related papers: A High-resolution Clock Phase Shifter Circuitry fo…

The upgrade of the ATLAS Liquid Argon Calorimeter readout system calls for the development of radiation tolerant, high speed and low power serializer ASIC. We have designed a phase locked loop using a commercial 0.25 um Silicon-on-Sapphire…

This paper present high precision halfwave rectifier circuit in dual phase output mode by 0.5 micrometer CMOS technology, plus or minus 1.5 V low voltage, it has received input signal and sent output current signal, respond in high…

The phase averaging reference line system provides the RF phase reference, LO and clock signals to the LLRF and other accelerator sub-systems. The PIP-II linac has RF systems at three frequencies - 162.5 MHz, 325 MHz and 650 MHz. A…

We present the implementation and verification of an in-pixel automatic threshold calibration circuit for the CMS Endcap Timing Layer (ETL) in the High-Luminosity LHC upgrade. The discriminator threshold of the ETL readout chip (ETROC)…

We present the characterization of a readout Application-Specific Integrated Circuit (ASIC) for the CMS Endcap Timing Layer (ETL) of the High-Luminosity LHC upgrade with charge injection. The ASIC, named ETROC and developed in a 65 nm CMOS…

The design of a high-precision time-to-digital converter (TDC) based on a multiphase clock implemented using a single field-programmable gate array is discussed in this paper. The TDC can increase the resolution of the measurement by using…

Switched capacitor arrays (SCA) ASICs are becoming more and more popular for the readout of detector signals, since the sampling frequency of typically several gigasamples per second allows excellent pile-up rejection and time measurements.…

This paper presents a low-jitter hybrid voltage level shifter (HVLS) suitable for high-speed applications. The proposed architecture offers the advantage of cross-coupled feedback to simultaneously generate two voltage domain signals with…

High-performance phase control units are crucial in beamforming technology, which has gained substantial attention for its ability to manipulate the wireless propagation environment, thereby enhancing capacity and coverage in communication…

The growing maturity of photonic integrated circuit (PIC) fabrication technology enables the high integration of an increasing number of optical components onto a single chip. With the incremental circuit complexity, the calibration of…

Optical phase shifters are extensively used in integrated optics not only for telecom and datacom applications, but also for sensors and quantum computing. While various active solutions have been demonstrated, progress in passive phase…

Visible-wavelength very large-scale integration (VLSI) photonic circuits have potential to play important roles in quantum information and sensing technologies. The realization of scalable, high-speed, and low-loss photonic mesh circuits…

We design a resistive heater optimized for efficient and low-loss optical phase modulation in a silicon-on-insulator (SOI) waveguide and characterize the fabricated devices. Modulation is achieved by flowing current perpendicular to a new…

This paper presents a mixed-mode delay-locked loop (MM-DLL) with binary search (BS) locking, designed to cover a broad frequency range from 533 MHz to 4.26 GHz. The BS locking scheme optimizes the locking time, reducing it from a linear to…

This letter presents a 360{\deg} phase detector cell for performing phase-shift measurements on multiple output systems. An analog phase detector, capable of detecting a maximum range of {\pm}90{\deg}, has been used to perform a double…

This paper presents an architecture of high-resolution delay generator implemented in a single field programmable gate array (FPGA) chip by exploiting the method of utilizing dedicated carry chains. It serves as the core component in…

This paper proposes a high-speed transceiver-based method for implementing a digital-to-time converter (DTC). A real-time decoding technique is introduced to inject time information into high-speed pattern data. The stability of the…

In TDC testing or timing system implementation tasks, it is often desirable to generate signal pulses with fine adjustable time intervals. In delay cell-based schemes, the time adjustment steps are limited by the propagation delays of the…

In this brief, we present a low-loss mechanically reconfigurable phase shifter implemented in gap-waveguide technology for mm-wave frequencies. The proposed design gives a practical implementation of tuning elements inside the waveguide…

We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low-Power…