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In recent years, Compute-in-memory (CiM) architectures have emerged as a promising solution for deep neural network (NN) accelerators. Multiply-accumulate~(MAC) is considered a {\textit de facto} unit operation in NNs. By leveraging the…

Up to the present, the wave union method can achieve the best timing performance in FPGA based TDC designs. However, it should be guaranteed in such a structure that the non-thermometer code to binary code (NTH2B) encoding process should be…

Time interleaved analog-to-digital conversion (TIADC) based on parallelism is an effective way to meet the requirement of the ultra-fast waveform digitizer beyond Gsps. Different methods to correct the mismatch errors among different…

High-speed high-resolution Analog-to-Digital Conversion is the key part for waveform digitization in physics experiments and many other domains. This paper presents a new fully digital correction of mismatch errors among the channels in…

The rapid scaling of large language models (LLMs) exacerbates communication bottlenecks in AI data centers (AIDCs). To overcome this, optical circuit switches (OCS) are increasingly adopted for their superior bandwidth capacity and energy…

In this work, we propose a deep learning (DL)-based approach that integrates a state-of-the-art algorithm with a time-frequency (TF) learning framework to minimize overall latency. Meeting the stringent latency requirements of 6G orthogonal…

Most methodologies for modeling Transmission Line (TL) based channels define the input-output relationship in the frequency domain (FD) and handle the TL resorting to a two-port network (2PN) formalism. These techniques have not yet been…

One of the main novelties in 5G is the flexible Time Division Duplex (TDD) frame, which allows adaptation to the latency requirements. However, this flexibility is not sufficient to support heterogeneous latency requirements, in which…

Integrating time-frequency resource conversion (TFRC), a new network resource allocation strategy, with call admission control can not only increase the cell capacity but also reduce network congestion effectively. However, the optimal…

We present a method for the evaluation, at the first level of trigger, of logical conditions with high time resolution, using the digitized times of fast signals delivered in the detectors of high rate experiments. We describe a…

The burgeoning interest within the space community in digital beamforming is largely attributable to the superior flexibility that satellites with active antenna systems offer for a wide range of applications, notably in communication…

Dynamic Time-division duplex (TDD) can provide efficient and flexible splitting of the common wireless cellular resources between uplink (UL) and downlink (DL) users. In this paper, the UL/DL optimization problem is formulated as a…

The bidirectional Fano algorithm (BFA) can achieve at least two times decoding throughput compared to the conventional unidirectional Fano algorithm (UFA). In this paper, bidirectional Fano decoding is examined from the queuing theory…

Phase change memory (PCM) has recently emerged as a promising technology to meet the fast growing demand for large capacity memory in computer systems, replacing DRAM that is impeded by physical limitations. Multi-level cell (MLC) PCM…

Present state of the art applications in the area of high energy physics experiments (HEP), radar communication, satellite communication and bio medical instrumentation require fault resilient data acquisition (DAQ) system with the data…

We report on the development of a novel FPGA-based Time-to-Digital Converter and its implementation in a detection chain that records the coordinates of single particles along three dimensions. The detector is composed of Micro-Channel…

With the new generation of the RPC, it is possible to work with induced signals of hundreds $\mu V$, hence the front-end electronics is an important and delicate part of the detector in order to get a detectable signal. The electronic chain…

A new TDC-chip is under development for the COMPASS experiment at CERN. The ASIC, which exploits the 0.6 micrometer CMOS sea-of-gate technology, will allow high resolution time measurements with digitization of 75 ps, and an unprecedented…

In this paper, we consider the issue of throughput and packet drop rate (PDR) optimization as two performance metrics for delay sensitive applications in network coded time division duplex (TDD) satellite systems with large round trip times…

The design and performance of wave union TDC implemented in a Lattice CertusPro-NX FPGA is discussed. This FPGA is available for radiation tolerant applications. The TDC is implemented with 16-channels and a 200 MHz reference clock. Each…