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As transistor dimensions continue to shrink, binary devices are rapidly approaching their fundamental limits in power density. In response, multi-valued systems have attracted significant attention due to their enhanced information density.…

Molecular Networks · Quantitative Biology 2026-04-28 Enqiang Zhu , Peize Qiu , Xianhang Luo , Chanjuan Liu , Jin Xu

We consider the problem of constructing fast and small binary adder circuits. Among widely-used adders, the Kogge-Stone adder is often considered the fastest, because it computes the carry bits for two $n$-bit numbers (where $n$ is a power…

Hardware Architecture · Computer Science 2017-01-19 Stephan Held , Sophie Theresa Spirkl

Approximate computing is emerging as an alternative to accurate computing due to its potential for realizing digital circuits and systems with low power dissipation, less critical path delay, and less area occupancy for an acceptable…

Hardware Architecture · Computer Science 2018-01-19 P Balasubramanian

Reversible circuits have applications in digital signal processing, computer graphics, quantum computation and cryptography. In this paper, a generalized k*k reversible gate family is proposed and a 3*3 gate of the family is discussed.…

Hardware Architecture · Computer Science 2010-08-20 Md. Rafiqul Islam , Md. Saiful Islam , Muhammad Rezaul Karim , Abdullah Al Mahmud , Hafiz Md. Hasan Babu

In this paper, an improved GEF fast addition algorithm is proposed. The proposed algorithm reduces time and memory space. In this algorithm, carry is calculated on the basis of arrival timing of the operand's bits without overhead of…

Data Structures and Algorithms · Computer Science 2013-04-09 Md. Mizanur Rahman , Md. Shahadat Hossain , Md. Rakib Hasan , M. M. A. Hashem

This paper shows how to design efficient arithmetic elements out of quantum gates using "carry-save" techniques borrowed from classical computer design. This allows bit-parallel evaluation of all the arithmetic elements required for Shor's…

Quantum Physics · Physics 2007-05-23 Phil Gossett

We compare the implementation of a 8x8 bit multiplier with two different implementations of a 4x4 quaternary digit multiplier. Interfacing this binary multiplier with quaternary to binary decoders and binary to quaternary encoders leads to…

Hardware Architecture · Computer Science 2020-05-07 Daniel Etiemble

This paper proposes a Low-Power, Energy Efficient 4-bit Binary Coded Decimal (BCD) adder design where the conventional 4-bit BCD adder has been modified with the Clock Gated Power Gating Technique. Moreover, the concept of DVT (Dual-vth)…

Hardware Architecture · Computer Science 2016-11-18 Dipankar Saha , Subhramita Basak , Sagar Mukherjee , C. K. Sarkar

When numbers are added in base $b$ in the usual way, carries occur. If two random, independent 1-digit numbers are added, then the probability of a carry is $\frac{b-1}{2b}$. Other choices of digits lead to less carries. In particular, if…

Combinatorics · Mathematics 2012-09-07 Noga Alon

This paper presents the designs of asynchronous early output dual-bit full adders without and with redundant logic (implicit) corresponding to homogeneous and heterogeneous delay-insensitive data encoding. For homogeneous delay-insensitive…

Hardware Architecture · Computer Science 2017-04-26 P Balasubramanian , K Prasad

High speed Full-Adder (FA) module is a critical element in designing high performance arithmetic circuits. In this paper, we propose a new high speed multiple-valued logic FA module. The proposed FA is constructed by 14 transistors and 3…

Hardware Architecture · Computer Science 2011-04-05 Ashkan Khatir , Shaghayegh Abdolahzadegan , Iman Mahmoudi

While many papers have proposed implementations of ternary adders and ternary multipliers, no comparisons have generally been done with the corresponding binary ones. We compare the implementations of binary and ternary adders and…

Hardware Architecture · Computer Science 2019-08-21 Daniel Etiemble

The main areas of research in VLSI system design include area, high speed, and power-efficient data route logic systems. The amount of time needed to send a carry through the adder limits the pace at which addition can occur in digital…

Hardware Architecture · Computer Science 2024-10-22 CH. Pallavi , C. Padma , R. Kiran Kumar , T. Suguna , C. Nalini

The Dadda algorithm is a parallel structured multiplier, which is quite faster as compared to array multipliers, i.e., Booth, Braun, Baugh-Wooley, etc. However, it consumes more power and needs a larger number of gates for hardware…

Systems and Control · Electrical Eng. & Systems 2023-07-13 Muteen Munawar , Zain Shabbir , Muhammad Akram

In the context of coded caching in the $K$-user BC, our work reveals the surprising fact that having multiple ($L$) transmitting antennas, dramatically ameliorates the long-standing subpacketization bottleneck of coded caching by reducing…

Information Theory · Computer Science 2018-02-12 Eleftherios Lampiris , Petros Elia

Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction,…

Hardware Architecture · Computer Science 2011-10-10 Sunil Gavaskar Reddy , Rajendra prasad

Carbon Nanotube Field Effect Transistor (CNFET) is a promising new technology that overcomes several limitations of traditional silicon integrated circuit technology. In recent years, the potential of CNFET for analog circuit applications…

Emerging Technologies · Computer Science 2012-05-10 Ishit Makwana , Vitrag Sheth

In this paper, we study the different possibilities to add two vectors of digits of a given length $m$. Our results show that there are at least $2^{m-1}$ different additions of such vectors, while there exist only two types of addition…

Number Theory · Mathematics 2012-09-18 Peter Hellekalek

Back-propagation has been the workhorse of recent successes of deep learning but it relies on infinitesimal effects (partial derivatives) in order to perform credit assignment. This could become a serious issue as one considers deeper and…

Machine Learning · Computer Science 2015-11-26 Dong-Hyun Lee , Saizheng Zhang , Asja Fischer , Yoshua Bengio

We consider the fundamental problem of constructing fast circuits for the carry bit computation in binary addition. Up to a small additive constant, the carry bit computation reduces to computing an \aop, i.e., a formula of type $t_0 \land…

Data Structures and Algorithms · Computer Science 2019-10-28 Ulrich Brenner , Anna Hermann