Related papers: Two New CNTFET Quaternary Full Adders for Carry-Pr…

In Carry Propagate Adders, carry propagation is the critical delay. The most efficient scheme is to generate Cout0 (Cin=0) and Cout1(Cin=1) and multiplex the correct output according to Cin. For any radix, the carry output is always 0/1. We…

Here we describe the design details and performance of proposed Carry Propagate Adder based on GDI technique. GDI technique is power efficient technique for designing digital circuit that consumes less power as compare to most commonly used…

The implementation of a quaternary 1-digit adder composed of a 2-bit binary adder, quaternary to binary decoders and binary to quaternary encoders is compared with several recent implementations of quaternary adders. This simple…

We consider the problem of constructing fast and small parallel prefix adders for non-uniform input arrival times. This problem arises whenever the adder is embedded into a more complex circuit, e. g. a multiplier. Most previous results are…

Based on the ASIC layout level simulation of 7 types of adder structures each of four different sizes, i.e. a total of 28 adders, we propose expressions for the width of each of the three regions of the final Carry Propagate Adder (CPA) to…

Optimization techniques for decreasing the time and area of adder circuits have been extensively studied for years mostly in binary logic system. In this paper, we provide the necessary equations required to design a full adder in…

The MUX implementation of ternary half adders and full adders using predecessor and successor functions lead to the most efficient efficient implementation using the smallest transistor count. These designs are compared with the binary…

We compare N*N quaternary digit and 2N*2N bit CNTFET multipliers in terms of Worst case delay, Chip area, Power and Power Delay Product (PDP) for N=1, N=2 and N=4. Both multipliers use Wallace reduction trees. HSpice simulations with 32-nm…

Approximate computing has in recent times found significant applications towards lowering power, area, and time requirements for arithmetic operations. Several works done in recent years have furthered approximate computing along these…

This paper investigates the use of carbon nanotube field effect transistors (CNFETs) for the design of ternary full adder cells. The proposed circuits have been designed based on the unique properties of CNFETs such as having desired…

In this paper, we propose an efficient quantum carry-lookahead adder based on the higher radix structure. For the addition of two $n$-bit numbers, our adder uses $O(n)-O(\frac{n}{r})$ qubits and $O(n)+O(\frac{n}{r})$ T gates to get the…

This paper presents a new early output hybrid input encoded asynchronous full adder designed using dual-rail and 1-of-4 delay-insensitive data codes. The proposed full adder when cascaded to form a ripple carry adder (RCA) necessitates the…

Given any numeration system, we call carry propagation at a number $N$ the number of digits that are changed when going from the representation of $N$ to the one of $N+1$, and amortized carry propagation the limit of the mean of the carry…

An integer adder for integers in the binary representation is one of the basic operations of any digital processor. For adding two integers of N bits each, the serial adder takes as many clock ticks. For achieving higher speeds, parallel…

The paper presents a systematic study and implementation of a reconfigurable combinatorial multi-operand adder for use in Deep Learning systems. The size of carry changes with the number of operands and hence a reliable algorithm to…

When adding integers in base $m$, carries occur. The same happens modulo a generic integer $q$ when the set of digits is a complete set of residues modulo $m$ for some positive integer $m$ dividing $q$. In this paper we prove that…

Qutrit (or ternary) structures arise naturally in many quantum systems, particularly in certain non-abelian anyon systems. We present efficient circuits for ternary reversible and quantum arithmetics. Our main result is the derivation of…

This article presents novel high speed and low power full adder cells based on carbon nanotube field effect transistor (CNFET). Four full adder cells are proposed in this article. First one (named CN9P4G) and second one (CN9P8GBUFF)…

This article presents two area/latency optimized gate level asynchronous full adder designs which correspond to early output logic. The proposed full adders are constructed using the delay-insensitive dual-rail code and adhere to the…

This paper presents a ternary half adder and a 1-trit multiplier using carbon nanotube transistors. The proposed circuits are designed using pass transistor logic and dynamic logic. Ternary logic uses less connections than binary logic, and…