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In modern systems, DRAM-based main memory is significantly slower than the processor. Consequently, processors spend a long time waiting to access data from main memory, making the long main memory access latency one of the most critical…

Hardware Architecture · Computer Science 2016-11-01 Donghyuk Lee

Stochastic computing (SC) is an emerging computing technique that promises high density, low power, and error tolerant solutions. In SC, values are encoded as unary bitstreams and SC arithmetic circuits operate on one or more bitstreams. In…

Signal Processing · Electrical Eng. & Systems 2018-03-14 Vincent T. Lee , Armin Alaghi , Luis Ceze

Next-generation wireless technologies (for immersive-massive communication, joint communication and sensing) demand highly parallel architectures for massive data processing. A common architectural template scales up by grouping tens to…

Hardware Architecture · Computer Science 2025-07-08 Samuel Riedel , Yichao Zhang , Marco Bertuletti , Luca Benini

A superconducting loop stores persistent current without any ohmic loss, making it an ideal platform for energy efficient memories. Conventional superconducting memories use an architecture based on Josephson junctions (JJs) and have…

The performance of superconducting quantum circuits for quantum computing has advanced tremendously in recent decades; however, a comprehensive understanding of relaxation mechanisms does not yet exist. In this work, we utilize a multimode…

To support emerging applications ranging from holographic communications to extended reality, next-generation mobile wireless communication systems require ultra-fast and energy-efficient baseband processors. Traditional complementary…

Signal Processing · Electrical Eng. & Systems 2023-08-22 Qunsong Zeng , Jiawei Liu , Mingrui Jiang , Jun Lan , Yi Gong , Zhongrui Wang , Yida Li , Can Li , Jim Ignowski , Kaibin Huang

Increasing circuit complexity within quantum systems based on superconducting qubits necessitates high connectivity while retaining qubit coherence. Classical micro-electronic systems have addressed interconnect density challenges by using…

In quantum computing architectures, one important factor is the trade-off between the need to couple qubits to each other and to an external drive and the need to isolate them well enough in order to protect the information for an extended…

Quantum Physics · Physics 2021-01-29 Kasra Sardashti , Matthieu C. Dartiailh , Joseph Yuan , Sean Hart , Patryk Gumann , Javad Shabani

Large-capacity Content Addressable Memory (CAM) is a key element in a wide variety of applications. The inevitable complexities of scaling MOS transistors introduce a major challenge in the realization of such systems. Convergence of…

Mesoscale and Nanoscale Physics · Physics 2015-03-17 Kamran Eshraghian , Kyoung Rok Cho , Omid Kavehei , Soon-Ku Kang , Derek Abbott , Sung-Mo Steve Kang

The increasing computational demand of Convolutional Neural Networks (CNNs) necessitates energy-efficient acceleration strategies. Compute-in-Memory (CIM) architectures based on Resistive Random Access Memory (RRAM) offer a promising…

Signal Processing · Electrical Eng. & Systems 2025-07-25 José Cubero-Cascante , Rebecca Pelke , Noah Flohr , Arunkumar Vaidyanathan , Rainer Leupers , Jan Moritz Joseph

Conformer models maintain a large number of internal states, the vast majority of which are associated with self-attention layers. With limited memory bandwidth, reading these from memory at each inference step can slow down inference. In…

Computation and Language · Computer Science 2023-04-04 Rami Botros , Anmol Gulati , Tara N. Sainath , Krzysztof Choromanski , Ruoming Pang , Trevor Strohman , Weiran Wang , Jiahui Yu

Synaptic delay parameterization of neural network models have remained largely unexplored but recent literature has been showing promising results, suggesting the delay parameterized models are simpler, smaller, sparser, and thus more…

A novel framework for performance analysis and code design is proposed to address the sneak path (SP) problem in resistive random-access memory (ReRAM) arrays. The main idea is to decompose the ReRAM channel, which is both non-ergodic and…

Information Theory · Computer Science 2024-12-10 Guanghui Song , Meiru Gao , Ying Li , Bin Dai , Kui Cai

In this paper, a simple memory limited transmitter for molecular communication is proposed, in which information is encoded in the diffusion rate of the molecules. Taking advantage of memory, the proposed transmitter reduces the ISI problem…

Information Theory · Computer Science 2014-10-30 Mohammad Movahednasab , Mehdi Soleimanifar , Amin Gohari , Masoumeh Nasiri Kenari , Urbashi Mitra

Over the past two decades, the storage capacity and access bandwidth of main memory have improved tremendously, by 128x and 20x, respectively. These improvements are mainly due to the continuous technology scaling of DRAM (dynamic…

Hardware Architecture · Computer Science 2017-12-25 Kevin K. Chang

Superconducting quantum computer is manufactured based on semiconductor process which makes qubits integration possible. At the same time, this kind of qubit exhibits high performance fidelity, de-coherence time, scalability and requires a…

Signal Processing · Electrical Eng. & Systems 2018-06-12 Jin Lin , Fu-Tian Liang , Yu Xu , Li-Hua Sun , Cheng Guo , Sheng-Kai Liao , Cheng-Zhi Peng

Superconducting integrated circuit (SIC) is a promising "beyond-CMOS" device technology enables speed-of-light, nearly lossless communications to advance cryogenic (4 K or lower) computing. However, the lack of large-area superconducting IC…

A robust cryogenic infrastructure in form of a wired, thermally optimized dilution refrigerator is essential for present and future solid-state based quantum processors. Here, we engineer an extensible cryogenic setup, which minimizes…

Superconducting qubits have been used in the most advanced demonstrations of quantum information processing, and they can be manufactured at-scale using proven semiconductor techniques. This makes them one of the leading technologies in the…

By supporting the access of multiple memory words at the same time, Bit-line Computing (BC) architectures allow the parallel execution of bit-wise operations in-memory. At the array periphery, arithmetic operations are then derived with…

Hardware Architecture · Computer Science 2022-09-14 Marco Rios , Flavio Ponzina , Alexandre Levisse , Giovanni Ansaloni , David Atienza