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Distributed hardware of acoustic sensor networks bears inconsistency of local sampling frequencies, which is detrimental to signal processing. Fundamentally, sampling rate offset (SRO) nonlinearly relates the discrete-time signals acquired…
Two-channel modulo analog-to-digital converters (ADCs) enable high-dynamic-range signal sensing at the Nyquist rate per channel, but existing designs quantise both channel outputs independently, incurring redundant bitrate costs. This paper…
Differing from synchronous generators, there are lack of physical laws governing the synchronization dynamics of voltage-source converters (VSCs). The widely used phase-locked loop (PLL) plays a critical role in maintaining the synchronism…
Data-driven methods enable online assessment of error states in magnetic-array-type current sensors, and long-term measurement stability can be enhanced through further self-error correction. However, when the magnetic-array-type current…
Digital-analog quantum computation aims to reduce the currently infeasible resource requirements needed for near-term quantum information processing by replacing sequences of one- and two-qubit gates with a unitary transformation generated…
An inevitable consequence of the global power system transition towards nearly 100% renewable-based generation is the loss of conventional bulk generation by synchronous machines, their inertia, and accompanying frequency and voltage…
The power consumption of high-speed, high-resolution analog to digital converters (ADCs) is a limiting factor in implementing large-bandwidth mm-wave communication systems. A mitigating solution, which has drawn considerable recent…
Telecommunication data is being used increasingly in urban mobility applications around the world. Despite its ubiquity and usefulness, technical difficulties arise when using Packet-Switched Charging Data Records (CDR), since its main…
This paper analyzes the performance of multicell massive multiple-input and multiple-output (MIMO) systems with variable-resolution analog-to-digital converters (ADCs). In such an architecture, each ADC uses arbitrary quantization…
Current-fed half bridge converter with bidirectional switches on ac side and a full bridge converter on dc side of a high frequency transformer is an optimal topology for single stage galvanically isolated ac-dc converter for onboard…
Input current estimation is indispensable in the sensorless control algorithms for the problem of power factor compensation (PFC) of an AC-DC boost converter. The system estimator design is challenged by the bilinear form dynamics and…
Many state-of-the-art neural network-based source separation systems use the averaged Signal-to-Distortion Ratio (SDR) as a training objective function. The basic SDR is, however, undefined if the network reconstructs the reference signal…
Analog-to-digtial (A/D) conversion plays a crucial role when it comes to the design of energy-efficient and fast signal processing systems. As its complexity grows exponentially with the number of output bits, significant savings are…
The renewable energy is connected to the power grid through power electronic converters, which are lack of make the inertia of synchronous generator/machine (SM) be lost. The increasing penetration of renewable energy in power system…
High data rates require vast bandwidths, that can be found in the sub-THz band, and high sampling frequencies, which are predicted to lead to a problematically high analog-to-digital converter (ADC) power consumption. It was proposed to use…
This paper presents a novel Sliding Mode Control (SMC) algorithm to handle mismatched uncertainties in systems via a novel Self-Learning Disturbance Observer (SLDO). A computationally efficient SLDO is developed within a framework of…
Analog in-memory computing (AIMC) is an energy-efficient alternative to digital architectures for accelerating machine learning and signal processing workloads. However, its energy efficiency is limited by the high energy cost of the column…
This paper presents a discrete-time analog frontend for an analog-to-digital (ADC) based equalizers. The frontend uses a discrete-time linear equalizer (DTLE) and ultralow-power 4-bit time-interleaved charge-steering flash ADC. The DTLE…
In this work, we describe a novel method of training an embedding-matching word-level connectionist temporal classification (CTC) automatic speech recognizer (ASR) such that it directly produces word start times and durations, required by…
Zero-delay transmission of a Gaussian source over an additive white Gaussian noise (AWGN) channel is considered with a one-bit analog-to-digital converter (ADC) front end and a correlated side information at the receiver. The design of the…