Related papers: High-performance and Low-power Transistors Based o…
Metal-mediated exfoliation has been demonstrated as a promising approach for obtaining large-area flakes of 2D materials to fabricate prototypical nanoelectronics. However, several processing challenges related to organic contamination at…
In this paper we propose two transistor concepts based on lateral heterostructures of monolayer MoS$_2$, composed of adjacent regions of 1T (metallic) and 2H (semiconducting) phases, inspired by recent research showing the possibility to…
Ultra-thin (UT) oxide semiconductors are promising candidates for back-end-of-line (BEOL) compatible transistors and monolithic three-dimensional integration. Experimentally, UT indium oxide (In$_2$O$_3$) field-effect transistors (FETs)…
Field-effect transistors (FETs) with non-covalently functionalised molybdenum disulfide (MoS2) channels grown by chemical vapour deposition (CVD) on SiO2 are reported. The dangling-bond-free surface of MoS2 was functionalised with a…
Ballistic transport characteristics of metal-oxide semiconductor field effect transistors (MOSFETs) based on anisotropic two-dimensional (2-D) materials monolayer HfS2 and phosphorene are explored through quantum transport simulations. We…
Two-dimensional ferroelectric materials are beneficial for power-efficient memory devices and transistor applications. Here, we predict out-of-plane ferroelectricity in a new family of buckled metal oxide (MO; M: Ge, Sn, Pb) monolayers with…
A new two-dimensional (2D) layered material, namely, titanium trisulfide (TiS$_3$) monolayer sheet, is predicted to possess desired electronic properties for nanoelectronic applications. On basis of the first-principles calculations within…
We demonstrate the design, fabrication, and characterization of wafer-scale, zero-bias power detectors based on two-dimensional MoS$_2$ field effect transistors (FETs). The MoS$_2$ FETs are fabricated using a wafer-scale process on 8 $\mu$m…
Nanoscale transistors require aggressive reduction of all channel dimensions: length, width, and thickness. While monolayer two-dimensional semiconductors (2DS) offer ultimate thickness scaling, good performance has largely been achieved…
Sub-1-nm gate length $MoS_2$ transistors have been experimentally fabricated, but their device performance limit remains elusive. Herein, we explore the performance limits of the sub-1-nm gate length monolayer (ML) $MoS_2$ transistors…
Two-dimensional (2D) semiconductors have been suggested both for ultimately-scaled field-effect transistors (FETs) and More-than-Moore nanoelectronics. However, these targets can not be reached without accompanying gate insulators which are…
We report a monolithic bidirectional dual-gate metal-oxide-semiconductor field effect transistor (MOSFET) fabricated on epitaxially grown beta-Ga2O3, demonstrating efficient two-way conduction and blocking. It features two independently…
The demands of modern electronic components require advanced computing platforms for efficient information processing to realize in-memory operations with a high density of data storage capabilities towards developing alternatives to von…
Advancing complementary metal-oxide-semiconductor (CMOS) technology into the sub-1-nm angstr\"om-scale technology nodes is expected to involve alternative semiconductor channel materials, as silicon transistors encounter severe performance…
Ferroelectric field-effect transistors (FeFET) with two-dimensional (2D) semiconductor channels are promising low-power, embedded non-volatile memory (NVM) candidates for next-generation in-memory computing. However, the performance of…
The performance limits of monolayer transition metal dichalcogenide transistors are examined with a ballistic MOSFET model. Using ab-initio theory, we calculate the band structures of two-dimensional (2D) transition metal dichalco-genide…
While 2D materials have enormous potential for future device technologies, many challenges must be overcome before they can be deployed at an industrial scale. One of these challenges is identifying the right semiconductor/insulator…
The continuous scaling of semiconductor technology has pushed the footprint of logic devices below 50 nm. Currently, logic standard cells with one single fin are being investigated to increase the integration density, although such options…
Ballistic device performance of monolayer black phosphorous (BP) field-effect transistors (FET) is investigated in this work. Due to the anisotropic effect mass of the carriers, the ON-state current is dependent on the transport direction.…
Large capacitance enhancement is useful for increasing the gate capacitance of field-effect transistors (FETs) to produce low-energy-consuming devices with improved gate controllability. We report strong capacitance enhancement effects in a…