Related papers: A 20 Gbps PAM4 Data Transmitter ASIC for Particle …

This paper presents the design and test results of a Gigabit Cable Receiver ASIC called GBCR for the HL-LHC upgrade of the ATLAS Inner Tracker (ITk) pixel detector. Three prototypes (GBCR1, GBCR2, and GBCR3) have been designed in the…

For the High-Luminosity phase of LHC, the ATLAS experiment is proposing the addition of a High Granularity Timing Detector (HGTD) in the forward region to mitigate the effects of the increased pile-up. The chosen detection technology is Low…

Tunable lasers emitting at a 2-3 $\mu$m wavelength range and compatible with photonic integration platforms are of great interest for sensing applications. To this end, combining GaSb-based semiconductor gain chips with Si$_3$N$_4$ photonic…

The next generation of MAPS for future tracking detectors will have to meet stringent requirements placed on them. One such detector is the ALICE ITS3 that aims to be very light at 0.07% X/X$_{0}$ per layer and have a low power consumption…

Silicon has attracted attention as an inexpensive and scalable material system for photonic-electronic, system-on-chip development. For this, a platform with both photodetectors and modulators working at high speeds, with excellent…

Next-generation gamma-ray observatories aim to enable precision measurements in high-energy astrophysics using advanced semiconductor detector technologies. Meeting the scientific requirements of modern instruments demands detector systems…

This paper presents the uTCA4.0-based BPM electronics for PIP-II, featuring four 250 MSPS ADCs and a Xilinx UltraScale+ MPSoC FPGA with 10 GbE uplink. Design elements include signal conditioning, clock, and thermal management. The FPGA…

The Quad transimpedance and limiting amplifier (QTIA) is a 4-channel array optical receiver ASIC, developed using a 65 nm CMOS process. It is configurable between the bit rate of 2.56 Gbps and 10 Gbps per channel. QTIA offers careful…

This paper presents GBSense, an innovative compressed spectrum sensing system designed for GHz-bandwidth signals in dynamic spectrum access (DSA) applications. GBSense introduces an efficient approach to periodic nonuniform sampling,…

Beam Delivery Simulation (BDSIM) is a program that simulates the passage of particles in a particle accelerator. It uses a suite of standard high energy physics codes (Geant4, ROOT and CLHEP) to create a computational model of a particle…

We designed a versatile analog front-end chip, called LTARS, for TPC-applications, primarily targeted at dual-phase liquid Ar-TPCs for neutrino experiments and negative-ion $\mu$-TPCs for directional dark matter searches. Low-noise…

A broadband silicon polarization beam splitter (PBS) is proposed and experimentally demonstrated based on Floquet-engineered directional couplers. The total length of the coupling structure is 20 um . By periodically modulating the…

The measurement of the biological tissue's electrical impedance is an active research field that has attracted a lot of attention during the last decades. Bio-impedances are closely related to a large variety of physiological conditions;…

Particle-based simulations and point-cloud applications generate massive, irregular datasets that challenge storage, I/O, and real-time analytics. Traditional compression techniques struggle with irregular particle distributions and GPU…

HIPSR (HI-Pulsar) is a digital signal processing system for the Parkes 21-cm Multibeam Receiver that provides larger instantaneous bandwidth, increased dynamic range, and more signal processing power than the previous systems in use at…

The Bates Linear Accelerator uses six 4MW 2.856GHz RF transmitters. Phase drifts between the transmitters 12 klystrons of greater than 0.5 degree or any amplitude drifts compromise beam delivery and are a common occurrence. Machine…

A pico-second timing (PIST) front-end electronic chip has been developed using $55~\mathrm{nm}$ CMOS technology for future electron-positron collider experiments (namely Higgs factories). Extensive tests have been performed to evaluate the…

Consider an arbitrary network of communicating modules on a chip, each requiring a local signal telling it when to execute a computational step. There are three common solutions to generating such a local clock signal: (i) by deriving it…

This paper describes two research projects that develop new low-cost techniques for testing devices with multiple high-speed (2 to 5 Gbps) signals. Each project uses commercially available components to keep costs low, yet achieves…

A 3.8ps root mean square (RMS) time synchronization implemented in a 20nm fabrication process ultrascale kintex Field Programmable Gate Array (FPGA) is presented. The multichannel high-speed serial transceivers (e.g. GTH) play a key role in…