Related papers: A Sub-Picosecond Digitally-Controlled Phase Delay

We describe a low-cost system designed to monitor wander in digital clocks with a precision of $\le$ 1 ps. With this system we have shown that it is possible to track phase variations at the sub-picosecond level by adding noise to a…

The design of a high-precision time-to-digital converter (TDC) based on a multiphase clock implemented using a single field-programmable gate array is discussed in this paper. The TDC can increase the resolution of the measurement by using…

A high-resolution clock phase shifter is implemented to adjust the phase of multiple clocks at 40 MHz, 80 MHz, or 640 MHz in the ALTIROC chip. The phase shifter has a coarse-phase shifter and a fine-phase shifter to achieve a step size of…

This paper proposes and evaluates a novel architecture for a low-power Time-to-Digital Converter with high resolution, optimized for both integration in multichannel chips and high rate operation (40 Mconversion/s/channel). This converter…

A clock synchronizing circuit for repeaterless low swing interconnects is presented in this paper. The circuit uses a delay locked loop (DLL) to generate multiple phases of the clock, of which the one closest to the center of the eye is…

In preparation for HL-LHC operation a number of new detector systems are being constructed with timing precision on physics objects of <50 picoseconds. These time stamps will reduce the level of pileup induced backgrounds in this LHC phase…

A 33.6 ps LSB Time-to-Digital converter was designed in 130 nm BiCMOS technology. The core of the converter is a differential 9-stage ring oscillator, based on a multi-path architecture. A novel version of this design is proposed, along…

The prospect of pileup induced backgrounds at the High Luminosity LHC (HL-LHC) has stimulated intense interest in technology for charged particle timing at high rates. In contrast to the role of timing for particle identification, which has…

In FEL (Free-Electron Laser) accelerators, LLRF (Low-Level Radiofrequency) systems usually deploy feedback or feedforward algorithms requiring precise microwave measurement. The slow drift of the clock allocation network of LLRF…

In this paper we address the question how the control of delayed measured chaotic systems can be improved. Both unmodified OGY control and difference control can be successfully applied only for a certain range of Lyapunov numbers depending…

In most digital-to-time converter (DTC) based applications, apart from maintaining low integral non-linearity (INL), it is also required of the system to achieve a wide frequency translation range. To achieve this performance, we present a…

Time-to-digital converters (TDCs) are used in various fields, including high-energy physics. One advantage of implementing TDCs in field-programmable gate arrays (FPGAs) is the flexibility on the modification of the logics, which is useful…

The prospect of pileup induced backgrounds at the High Luminosity LHC (HL-LHC) has stimulated intense interest in technology for charged particle timing at high rates\cite{challenge}. In this paper I report on a framework for fast timing…

In TDC testing or timing system implementation tasks, it is often desirable to generate signal pulses with fine adjustable time intervals. In delay cell-based schemes, the time adjustment steps are limited by the propagation delays of the…

Time-to-Digital Converters (TDCs) are a crucial tool in a wide array of fields, in particular for quantum communication, where time taggers performance can severely affect the quality of the entire application. Nowadays, FPGA-based TDCs…

We demonstrate precision enhancements in a timekeeping device at constant power and regardless of the operation frequency. Our timekeeping device is a laser-driven coupled-cavity system sustaining limit cycles. We quantify the precision of…

The PhaseII Upgrades of CMS are being planned for the High Luminosity LHC (HL-LHC) era when the mean number of interactions per beam crossing ("in-time pileup") is expected to reach ~140-200. The potential backgrounds arising from…

This paper presents the design and testing of a time-stretching-based time-to-digital converter (TDC) implemented with discrete components. The TDC utilizes capacitor charging and discharging to achieve a time resolution of under 100 ps…

For the advancement of the understanding of timing systematics in pixelized readout chips and for the benefit of future fast timing detectors to aid 4D tracking technology in the HL-LHC, we have performed detailed studies of the timing…

A high precision and high resolution time-to-digital converter (TDC) implemented in a 40 nm fabrication process Virtex-6 FPGA is presented in this paper. The multi-chain measurements averaging architecture is used to overcome the resolution…