Related papers: A radiation tolerant clock generator for the CMS E…

A high-resolution clock phase shifter is implemented to adjust the phase of multiple clocks at 40 MHz, 80 MHz, or 640 MHz in the ALTIROC chip. The phase shifter has a coarse-phase shifter and a fine-phase shifter to achieve a step size of…

With the new generation of the RPC, it is possible to work with induced signals of hundreds $\mu V$, hence the front-end electronics is an important and delicate part of the detector in order to get a detectable signal. The electronic chain…

In most digital-to-time converter (DTC) based applications, apart from maintaining low integral non-linearity (INL), it is also required of the system to achieve a wide frequency translation range. To achieve this performance, we present a…

We present a gigabit transceiver prototype Application Specific Integrated Circuit (ASIC), GBCR, for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR is designed in a 65-nm CMOS technology and consists of four upstream…

This paper presents our low-latency Polar code encoders and decoders developed for the 2025 International Symposium on Topics in Coding (ISTC 2025) contest, which challenges participants to implement the fastest possible channel code…

CEA/IRFM is conducting R\&D efforts in order to validate the critical RF components of the 5 GHz ITER LHCD system, which is expected to transmit 20 MW of RF power to the plasma. Two 5 GHz 500 kW BeO pill-box type window prototypes have been…

Ultra-reliable low latency communication (URLLC) is a key part of 5G wireless systems. Achieving low latency necessitates codes with short blocklengths for which polar codes with successive cancellation list (SCL) decoding typically…

Clock generators are an essential and critical building block of any communication link, whether it be wired or wireless, and they are increasingly critical given the push for lower I/O power and higher bandwidth in Systems-on-Chip (SoCs)…

The ILD concept, one of two proposed detector concepts for the planned International Linear Collider (ILC), foresees a Time Projection Chamber (TPC) as the main tracking detector. The LCTPC (Linear Collider TPC) collaboration pursues R&D to…

The ALICE (A Large Ion Collider Experiment) Time Projection Chamber (TPC) at CERN LHC is presently equipped with Multi Wire Proportional Chambers (MWPCs). A gating grid prevents ions produced during the gas amplification from moving into…

Results of detailed simulations of the charge transfer inefficiency of a prototype serial readout CCD chip are reported. The effect of radiation damage on the chip operating in a particle detector at high frequency at a future accelerator…

With the ultimate goal of developing a pixel-based readout for a TPC at the ILC, a GridPix readout system consisting of one Timepix3 chip with an integrated amplification grid was embedded in a prototype detector. The performance was…

Fully Field Programmable Gate Array (FPGA)based digitizer for high-resolution time and energy measurement is an attractive low cost solution for the readout electronics in positron emission computed tomography (PET)detector. In recent…

The LHC will undergo a major upgrade starting in 2025 towards the High Luminosity LHC (HL-LHC) to increase the instantaneous luminosity by a factor of 5 to 7 compared to the nominal value. The Phase-II Upgrade (2025-2027) will require the…

The ALICE (A Large Ion Collider Experiment) experiment at the Large Hadron Collider (LHC) at CERN is dedicated to heavy ion physics to explore the structure of strongly interacting matter. The Time Projection Chamber (TPC) of ALICE is a…

We report on the performance of the first table-top prototype atomic clock based on coherent population trapping (CPT) resonances with parallel linearly polarized optical fields (lin||lin configuration). Our apparatus uses a vertical cavity…

In this paper, we present the design and test results of LOCx2-130, a low-power, low-latency, dual-channel transmitter ASIC for detector front-end readout. LOCx2-130 has two channels of encoders and serializers, and each channel operates at…

A compact low-level RF (LLRF) control system based on RF system-on-chip (RFSoC) technology has been designed for the Advanced Concept Compact Electron Linear-accelerator (ACCEL) program, which has challenging requirements in both RF…

The radiation hardness of passive CMOS pixel sensors fabricated in 150 nm LFoundry technology is investigated. CMOS process lines are especially of interest for large-scale silicon detectors as they offer high production throughput at…

Charge pump phase-locked loop with phase-frequency detector (CP-PLL) is an electrical circuit, widely used in digital systems for frequency synthesis and synchronization of the clock signals. In this paper a non-linear second-order model of…