Related papers: ACTreS: Analog Clock Tree Synthesis
In this paper, we focus on the design and verification of timed automata (TA). We introduce a new method for assisting construction and verification of TA models along with a tool implementing the proposed method, i.e., ATAC: Automated…
The design and measurement results of ultra-low power, fast 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) prototypes in 65 nm CMOS technology are presented. Eight prototype ADCs were designed using two…
Traditional risk assessments rely on manual audits and system scans, often causing operational disruptions and leaving security gaps. To address these challenges, this work presents Security Digital Twin-as-a-Service (SDT-aaS), a novel…
The reconstruction of charged particle trajectories is one of the most complex and CPU consuming parts of event processing in high energy experiments. At future hadron colliders such as the High-Luminosity Large Hadron Collider (HL-LHC) or…
Here in this paper we are presenting a digital system background technique for correcting the time offset error rate and gain mismatches in a time interleaved analog to digital converter system for N channel communication using 8 bit…
Recent advancements have demonstrated the significant potential of large language models (LLMs) in analog circuit design. Nevertheless, testbench construction for analog circuits remains manual, creating a critical bottleneck in achieving…
Partial resonance high frequency AC link converters are recognized to provide soft-switching, single-stage power conversion. They are highly reliable due to elimination of DC capacitors. Previous work has focused on proof of concept…
This paper presents a fully integrated second-order level-crossing sampling data converter for real-time data compression and feature extraction. Compared with level-sampling ADCs which sample at fixed voltage levels, the proposed circuits…
This paper presents an automated software toolchain for synthesizing hardware-implementable analog circuits that solve constrained optimization problems. The proposed toolchain supports nonlinear objective functions with linear and…
Despite the increasing adoption of Field-Programmable Gate Arrays (FPGAs) in compute clouds, there remains a significant gap in programming tools and abstractions which can leverage network-connected, cloud-scale, multi-die FPGAs to…
This paper addresses delay test for SOC devices with high frequency clock domains. A logic design for on-chip high-speed clock generation, implemented to avoid expensive test equipment, is described in detail. Techniques for on-chip clock…
The massive and large-scale design of foundational semiconductor integrated circuits (ICs) is crucial to sustaining the advancement of many emerging and future technologies, such as generative AI, 5G/6G, and quantum computing. Excitingly,…
Parallel real-time embedded applications can be modelled as directed acyclic graphs (DAGs) whose nodes model subtasks and whose edges model precedence constraints among subtasks. Efficiently scheduling such parallel tasks can be challenging…
Molecular design and synthesis planning are two critical steps in the process of molecular discovery that we propose to formulate as a single shared task of conditional synthetic pathway generation. We report an amortized approach to…
Many Embedded Systems are indeed Software Based Control Systems, that is control systems whose controller consists of control software running on a microcontroller device. This motivates investigation on Formal Model Based Design approaches…
Modeling system-level behaviors of intricate System-on-Chip (SoC) designs is crucial for design analysis, testing, and validation. However, the complexity and volume of SoC traces pose significant challenges in this task. This paper…
Trees are fundamental data structure for many areas of computer science and system engineering. In this report, we show how to ensure eventual consistency of optimistically replicated trees. In optimistic replication, the different replicas…
This paper presents an algorithmic framework for control synthesis of continuous dynamical systems subject to signal temporal logic (STL) specifications. We propose a novel algorithm to obtain a time-partitioned finite automaton from an STL…
We propose an idea of an electronic multi-channel arbitrary digital sequence generator with temporal granularity equal to a single clock cycle. We implement the generator with 32 channels using a low-cost ARM microcontroller and demonstrate…
In the last decades, various events have shown that electromechanical oscillations are a major concern for large interconnected Alternative Current (AC) power systems. DC segmentation - a method that consist in turning large AC grids into a…