Related papers: A Low-Power, Low-Latency, Dual-Channel Serializer …
In this paper, we present the design and test results of LOCx2-130, a low-power, low-latency, dual-channel transmitter ASIC for detector front-end readout. LOCx2-130 has two channels of encoders and serializers, and each channel operates at…
In this paper, we present the design and test results of LOCx2, a transmitter ASIC for the ATLAS Liquid Argon Calorimeter trigger upgrade. LOCx2 consists of two channels and each channel encodes ADC data with an overhead of 14.3% and…
A serializer ASIC and a VCSEL driver ASIC are needed for the front-end optical data transmission in the ATLAS liquid argon calorimeter readout phase-I upgrade. The baseline ASICs are the serializer LOCx2 and the VCSEL driver LOCld, designed…
We present the design and the test results of a dual-channel Vertical-Cavity Surface-Emitting Laser (VCSEL) driver ASIC LOCld65 for detector front-end readout. LOCld65 is designed in a commercial 65-nm CMOS technology with a power supply of…
We present the design and test results of two optical data transmission ASICs for the High-Luminosity LHC (HL-LHC) experiments. These ASICs include a two-channel serializer (LOCs2) and a single-channel Vertical Cavity Surface Emitting Laser…
We report on the design of a serializer ASIC to be used in the ATLAS forward muon detector for trigger data transmission. We discuss the performance of a prototype chip covering power dissipation, latency and stable operating line rate.…
We have been developing a serializer application-specific integrated circuit (ASIC) based on a commercial 0.25-{\mu}m silicon-on-sapphire (SOS) CMOS technology for the ATLAS liquid argon calorimeter front-end electronics upgrade. The first…
Three generations of full-custom analog integrated circuits designed for low-power, high-speed sampling of Radio-Frequency (RF) transients in excess of the Nyquist minimum have been developed. These 0.25$\mu m$ CMOS devices are denoted the…
The upgrade of the ATLAS Liquid Argon Calorimeter readout system calls for the development of radiation tolerant, high speed and low power serializer ASIC. We have designed a phase locked loop using a commercial 0.25 um Silicon-on-Sapphire…
A 64-channel mixed-mode ASIC, suitable for particle detectors of large dynamic range and high capacitance up to hundreds of pF, is presented here. Each channel features an analogue front-end for signal amplification and filtering, and a…
The upgrade of ATLAS Liquid Argon Calorimeter (LAr) Phase-1 trigger requires high-speed, low-latency data transmission to read out the Lar Trigger Digitizer Board (LTDB). A dual-channel transmitter ASIC LOCx2 have been designed and…
We designed a versatile analog front-end chip, called LTARS, for TPC-applications, primarily targeted at dual-phase liquid Ar-TPCs for neutrino experiments and negative-ion $\mu$-TPCs for directional dark matter searches. Low-noise…
We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital…
This paper presents the NSX front-end ASIC, being developed to read charge signals from the HEMA and WFM X-ray detectors for the STROBE-X mission. The ASIC reads out signals from up to 64 anodes of linear Silicon Drift Detectors (SDDs).…
We present two prototypes of a gigabit transceiver ASIC, GBCR1 and GBCR2, both designed in a 65-nm CMOS technology for the ATLAS Inner Tracker Pixel Detector readout upgrade. The first prototype, GBCR1, has four upstream receiver channels…
A front-end readout electronics system has been developed for silicon strip detectors. The system uses an application specific integrated circuit (ASIC) ATHED to realize multi-channel E&T measurement. The slow control of ASIC chips is…
We have designed three ASICs for possible applications in the optical links of a new layer of pixel detector in the ATLAS experiment for the first phase of the LHC luminosity upgrade. The ASICs include a high-speed driver for the VCSEL, a…
This paper presents the design, implementation, and performance evaluation of LUCAS, a low-power, ultra-low jitter ASIC optimized for SiPM readout in Time-of-Flight Computed Tomography (ToF-CT) applications. Leveraging a novel preamplifier…
We present our latest ASIC, which is used for the readout of Cadmium Telluride double-sided strip detectors (CdTe DSDs) and high spectroscopic imaging. It is implemented in a 0.35 um CMOS technology (X-Fab XH035), consists of 64 readout…
For the High-Luminosity phase of LHC, the ATLAS experiment is proposing the addition of a High Granularity Timing Detector (HGTD) in the forward region to mitigate the effects of the increased pile-up. The chosen detection technology is Low…