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Modern OpenMP threading techniques are used to convert the MPI-only Hartree-Fock code in the GAMESS program to a hybrid MPI/OpenMP algorithm. Two separate implementations that differ by the sharing or replication of key data structures…

Distributed, Parallel, and Cluster Computing · Computer Science 2017-08-15 Vladimir Mironov , Yuri Alexeev , Kristopher Keipert , Michael D'mello , Alexander Moskovsky , Mark S. Gordon

This paper addresses the design of a partly-parallel cascaded FFT-IFFT architecture that does not require any intermediate buffer. Folding can be used to design partly-parallel architectures for FFT and IFFT. While many cascaded FFT-IFFT…

Hardware Architecture · Computer Science 2024-03-21 Keshab K. Parhi

Efficient number representation is essential for federated learning, natural language processing, and network measurement solutions. Due to timing, area, and power constraints, such applications use narrow bit-width (e.g., 8-bit) number…

Networking and Internet Architecture · Computer Science 2024-10-08 Itamar Cohen , Gil Einziger

Sparse Matricized Tensor Times Khatri-Rao Product (spMTTKRP) is the most time-consuming compute kernel in sparse tensor decomposition. In this paper, we introduce a novel algorithm to minimize the execution time of spMTTKRP across all modes…

Distributed, Parallel, and Cluster Computing · Computer Science 2023-10-17 Sasindu Wijeratne , Rajgopal Kannan , Viktor Prasanna

Dynamic Parallelism (DP) is a runtime feature of the GPU programming model that allows GPU threads to execute additional GPU kernels, recursively. Apart from making the programming of parallel hierarchical patterns easier, DP can also…

Distributed, Parallel, and Cluster Computing · Computer Science 2022-06-07 Felipe A. Quezada , Cristóbal A. Navarro , Miguel Romero , Cristhian Aguilera

Intensive computation is entering data centers with multiple workloads of deep learning. To balance the compute efficiency, performance, and total cost of ownership (TCO), the use of a field-programmable gate array (FPGA) with…

Computer Vision and Pattern Recognition · Computer Science 2019-09-19 Xiaoyu Yu , Yuwei Wang , Jie Miao , Ephrem Wu , Heng Zhang , Yu Meng , Bo Zhang , Biao Min , Dewei Chen , Jianlin Gao

In recent years fused-multiply-add (FMA) units with lower-precision multiplications and higher-precision accumulation have proven useful in machine learning/artificial intelligence applications, most notably in training deep neural networks…

Mathematical Software · Computer Science 2019-04-16 Greg Henry , Ping Tak Peter Tang , Alexander Heinecke

In recent years, there is a surge on machine learning applications in industry. Many of them are based on popular AI frameworks like Tensorflow, Torch, Caffe, or MxNet, etc, and are enpowered by accelerator platforms such as GPUs. One…

Distributed, Parallel, and Cluster Computing · Computer Science 2018-11-14 Guoping Long , Jun Yang , Kai Zhu , Wei Lin

FPGA accelerators on the NIC enable the offloading of expensive packet processing tasks from the CPU. However, FPGAs have limited resources that may need to be shared among diverse applications, and programming them is difficult. We present…

Vortex, a newly proposed open-source GPGPU platform based on the RISC-V ISA, offers a valid alternative for GPGPU research over the broadly-used modeling platforms based on commercial GPUs. Similarly to the push originating from the RISC-V…

Hardware Architecture · Computer Science 2025-12-02 Giuseppe M. Sarda , Nimish Shah , Abubakr Nada , Debjyoti Bhattacharjee , Marian Verhelst

Sparse tensors appear in many large-scale applications with multidimensional and sparse data. While multidimensional sparse data often need to be processed on manycore processors, attempts to develop highly-optimized GPU-based…

Mathematical Software · Computer Science 2017-12-18 Bangtian Liu , Chengyao Wen , Anand D. Sarwate , Maryam Mehri Dehnavi

Scientific workflows are pipelines of interdependent tasks. They are increasingly executed on shared Kubernetes clusters via workflow engines such as Nextflow. Their energy consumption matters for both cost and sustainability. It is…

Distributed, Parallel, and Cluster Computing · Computer Science 2026-05-22 Philipp Thamm , Somayeh Mohammadi , Kathleen West , Knut Reinert , Lauritz Thamsen , Ulf Leser

Modern large language model workloads put increasing demands on parallel compute capability and on-chip memory capacity, while also stressing fine-grained data movement and synchronization. These trends motivate exploring and designing…

Hardware Architecture · Computer Science 2026-05-11 Yinrong Li , Zexin Fu , Yichao Zhang , Germain Haugou , Chi Zhang , Marco Bertuletti , Bowen Wang , Luca Benini

Fast Fourier transform (FFT) of large number of samples requires huge hardware resources of field programmable gate arrays (FPGA), which needs more area and power. In this paper, we present an area efficient architecture of FFT processor…

Hardware Architecture · Computer Science 2015-02-26 Atin Mukherjee , Amitabha Sinha , Debesh Choudhury

We show in this work that memory intensive computations can result in severe performance problems due to off-chip memory access and CPU-GPU context switch overheads in a wide range of deep learning models. For this problem, current…

Distributed, Parallel, and Cluster Computing · Computer Science 2021-12-20 Zhen Zheng , Pengzhan Zhao , Guoping Long , Feiwen Zhu , Kai Zhu , Wenyi Zhao , Lansong Diao , Jun Yang , Wei Lin

In this paper, we propose LoopLynx, a scalable dataflow architecture for efficient LLM inference that optimizes FPGA usage through a hybrid spatial-temporal design. The design of LoopLynx incorporates a hybrid temporal-spatial architecture,…

Hardware Architecture · Computer Science 2025-04-15 Jianing Zheng , Gang Chen

Gaussian processes are widely used in machine learning domains but remain computationally demanding, limiting their efficient scalability across emerging hardware platforms. The GPRat library addresses these challenges using the HPX…

Distributed, Parallel, and Cluster Computing · Computer Science 2026-05-29 Alexander Strack , Patrick Diehl , Dirk Pflüger

In this paper, we propose a high-performance RISC-V soft processor with an efficient fetch unit supporting the compressed instructions targeting on FPGA. The compressed instruction extension in RISC-V can reduce the program size by about…

Hardware Architecture · Computer Science 2020-11-24 Takuto Kanamori , Hiromu Miyazaki , Kenji Kise

FFT (fast Fourier transform) plays a very important role in many fields, such as digital signal processing, digital image processing and so on. However, in application, FFT becomes a factor of affecting the processing efficiency, especially…

Distributed, Parallel, and Cluster Computing · Computer Science 2017-07-25 Fan Zhang , Chen Hu , Qiang Yin , Wei Hu

Vision Transformers (ViTs) have established new performance benchmarks in vision tasks such as image recognition and object detection. However, these advancements come with significant demands for memory and computational resources,…

Hardware Architecture · Computer Science 2026-02-10 Cong Wang , Zexin Fu , Jiayi Huang , Shanshi Huang