Related papers: Analysis of Auto Zeroing Amplifier

Current-fed half bridge converter with bidirectional switches on ac side and a full bridge converter on dc side of a high frequency transformer is an optimal topology for single stage galvanically isolated ac-dc converter for onboard…

Based on an equivalent model for quantizers with noisy inputs recently presented in [35], we propose a method of digital dithering at the transmitter that may significantly reduce the resolution requirements of MIMO downlink Digital to…

A modular and scalable converter for medium voltage (MV) AC to low voltage (LV) DC power conversion is proposed; single-phase-modules (SPMs), each consisting of an active-front-end (AFE) stage and an isolated DC-DC stage, are connected in…

State-of-the-art in-memory computation has recently emerged as the most promising solution to overcome design challenges related to data movement inside current computing systems. One of the approaches to performing in-memory computation is…

Direct phase modulation via optical injection is a newly developed method for coding the phase of a gain-switched laser, which meets high requirements placed on transmitters for quantum key distribution: compactness, low losses,…

This paper proposes and evaluates a novel architecture for a low-power Time-to-Digital Converter with high resolution, optimized for both integration in multichannel chips and high rate operation (40 Mconversion/s/channel). This converter…

Dynamic comparators are an essential part of low-power analog to digital converters (ADCs) and are referred to as one of the most important building blocks in mixed mode circuits. The power consumption and accuracy of dynamic comparators…

The design and measurement results of ultra-low power, fast 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) prototypes in 65 nm CMOS technology are presented. Eight prototype ADCs were designed using two…

In this paper, we investigate hybrid analog/digital beamforming for multiple-input multiple-output (MIMO) systems with low-resolution analog-to-digital converters (ADCs) for millimeter wave (mmWave) communications. In the receiver, we…

We consider the stability and performance of a discrete-time control loop used as a dynamic nuller in the presence of a relatively large time delay in its feedback path. Controllers of this form occur in mm-wave telescopes using…

This work investigates the downlink performance of a multi-cell massive multiple-input multiple-output (MIMO) system that employs one-bit analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) in the receiving and…

This is a review paper updated from that presented for CAS 2004. Essentially, since then, commercial components have continued to extend their performance boundaries but the basic building blocks and the techniques for choosing the best…

A Low-Power Variable Gain (VG) mm-Wave Low Noise Amplifier (LNA) is designed and simulated in a 28-nm CMOS process. The LNA utilizes a simple, yet novel, technique presented in this paper to vary the small-signal output resistance to…

This paper presents an output capacitor-less low-dropout regulator (LDO) with a bias switching scheme for biomedical applications with dual-range load currents. Power optimization is crucial for systems with multiple activation modes such…

We propose a novel digital-to-analog converter (DAC) weighting architecture that statistically minimizes the distortion caused by random current mismatches. Unlike binary, thermometer-coded, and segmented DACs, the current weights of the…

In a high-speed coherent optical transmission system, typically the signals obtained at the receiver front-end are digitized using very high-speed ADCs and then processed in the digital domain to remove optical channel impairments. In this…

A series of simple and low-cost devices for switching, amplifying, and chirping diode lasers based on current modulation are presented. Direct modulation of diode laser currents is rarely sufficient to establish precise amplitude and phase…

A single channel 1.5GS/s 8-bit pipelined-SAR ADC utilizes a novel output level shifting (OLS) settling technique to reduce the power and enable low-voltage operation of the dynamic residue amplifier. The ADC consists of a 4-bit first stage…

A concept for a novel CMOS image sensor suited for analog image pre-processing is presented in this paper. As an example, an image restoration algorithm for reducing image noise is applied as image pre-processing in the analog domain. To…

This paper studies an architecture with digitally controllable gain and power consumption to mitigate the impact of process variations on CMOS low-noise amplifiers (LNAs). A \SI{130}{nm}, \SI{1.2}{V} LNA implementing the proposed…