Related papers: Negative Capacitance DG Junctionless FETs: A Charg…
Integrating ferroelectric negative capacitance (NC) into the field-effect transistor (FET) promises to break fundamental limits of power dissipation known as Boltzmann tyranny. However, realizing the stable static negative capacitance in…
In this paper, a two-dimensional analytical model of a laterally graded-channel triple-metal double-gate Junctionless Field Effect Transistor with hetero dielectric gate oxide stack consisting of SiO$_2$ and HfO$_2$ is derived. The model…
The elegant simplicity of the device concept and the urgent need for a new "transistor" at the twilight of Moore's law have inspired many researchers in industry and academia to explore the physics and technology of negative capacitance…
In this study, a SPICE model for negative capacitance vertical nanowire field-effect-transistor (NC VNW-FET) based on BSIM-CMG model and Landau-Khalatnikov (LK) equation was presented. Suffering from the limitation of short gate length…
Negative differential conductance (NDC) manifests as a significant characteristic of various underlying physics and transport processes in hybrid superconducting devices. In this work, we report the observation of gate-tunable NDC outside…
Vertical tunneling field-effect-transistor (FET) based on graphene heterojunctions with layers of hBN is simulated by self-consistent quantum transport simulations. It is found that the asymmetric p-type and n-type conduction is due to work…
In this paper, we develop an explicit model to predict the DC electrical behavior in ultra-thin surrounding gate junctionless nanowire FET. The proposed model takes into account 2D electrical and geometrical confinements of carrier charge…
Negative capacitance can be used to overcome the lower limit of subthreshold swing (SS) in field effect transistors (FETs), enabling ultralow-power microelectronics, though the concept of ferroelectric negative capacitance remains…
We report a bi-polar multiple periodic negative differential conductance (NDC) effect on a single cage-shaped Ru nanoparticle measured using scanning tunneling spectroscopy. This phenomenon is assigned to the unique multiply-connected cage…
The observation of room temperature sub-60 mV/dec subthreshold slope (SS) in MOSFETs with ferroelectric (FE) layers in the gate stacks or in series with the gate has attracted much attention. Recently, we modeled this effect in the…
We have presented a compact MOSFET model, which allows us to describe the I-V characteristics of irradiated long-channel and short-channel transistors in all operation modes at different measurement temperatures and interface trap…
We present a circuit-compatible compact model of the intrinsic capacitances of graphene field-effect transistors (GFETs). Together with a compact drain current model, a large-signal model of GFETs is developed combining both models as a…
Junctionless transistors made of silicon have previously been demonstrated experimentally and by simulations. Junctionless devices do not require fabricating an abrupt source-drain junction and thus can be easier to implement in aggressive…
In 2008, Salahuddin and Datta proposed that a ferroelectric material operating in the negative capacitance region could act as a step-up converter of the surface potential in a MOS structure, opening a new route for the realization of…
Recent measurements on ultra-thin body Negative Capacitance Field Effect Transistors have shown subthreshold behaviors that are not expected in a classical MOSFET. Specifically, subthreshold swing was found to decrease with increased gate…
The negative capacitance (NC) stabilization of a ferroelectric (FE) material can potentially provide an alternative way to further reduce the power consumption in ultra-scaled devices and thus has been of great interest in technology and…
We present a scaling theory of two-dimensional (2D) field effect transistors (FETs). For devices with channel thickness less than 4 nm, the device electrostatics is dominated by the physical gate oxide thickness and not the effective oxide…
Tri-gate ferroelectric FETs with Hf0.5Zr0.5O2 gate insulator for memory and neuromorphic applications are fabricated and characterized for multi-level operation. The conductance and threshold voltage exhibit highly linear and symmetric…
We analyze the distributions of electric potential and field, polarization and charge, and the differential capacitance of a silicon metal-oxide-ferroelectric field effect transistor (MOSFET), in which a gate insulator consists of thin…
Large capacitance enhancement is useful for increasing the gate capacitance of field-effect transistors (FETs) to produce low-energy-consuming devices with improved gate controllability. We report strong capacitance enhancement effects in a…