Related papers: Performance of a Front End prototype ASIC for pico…
This paper presents the design and characterisation of a front-end prototype ASIC for the ATLAS High Granularity Timing Detector, which is planned for the High-Luminosity phase of the LHC. This prototype, called ALTIROC1, consists of a…
The analog front-end for the Low Gain Avalanche Detector (LGAD) based precision timing application in the CMS Endcap Timing Layer (ETL) has been prototyped in a 65 nm CMOS mini-ASIC named ETROC0. Serving as the very first prototype of ETL…
We present the characterization of a readout Application-Specific Integrated Circuit (ASIC) for the CMS Endcap Timing Layer (ETL) of the High-Luminosity LHC upgrade with charge injection. The ASIC, named ETROC and developed in a 65 nm CMOS…
The development of detectors that provide high resolution in four dimensions has attracted wide-spread interest in the scientific community for applications in high-energy physics, nuclear physics, medical imaging, mass spectroscopy as well…
We present the first results from the HPSoC ASIC designed for readout of Ultra-fast Silicon Detectors. The 4-channel ASIC manufactured in 65 nm CMOS by TSMC has been optimized for 50 um thick AC-LGAD. The evaluation of the analog front end…
We present the design and characterization of the first full chain precision timing prototype ASIC, named ETL Readout Chip version 1 (ETROC1) for the CMS MTD endcap timing layer (ETL) upgrade. The ETL utilizes Low Gain Avalanche Diode…
For the high luminosity upgrade of the LHC at CERN, ATLAS is considering the addition of a High Granularity Timing Detector (HGTD) in front of the end cap and forward calorimeters at |z| = 3.5 m and covering the region 2.4 < |{\eta}| < 4 to…
Silicon-based fast time detectors have been widely used in high energy physics, nuclear physics, space exploration and other fields in recent years. However, silicon detectors often require complex low-temperature systems when operating in…
A monolithic silicon pixel ASIC prototype, produced in 2024 as part of the Horizon 2020 MONOLITH ERC Advanced project, was tested with a 120 GeV/c pion beam. The ASIC features a matrix of hexagonal pixels with a 100 \mu m pitch, read by…
The High-Granularity Timing Detector is a detector proposed for the ATLAS Phase II upgrade. The detector, based on the Low-Gain Avalanche Detector (LGAD) technology will cover the pseudo-rapidity region of $2.4<|\eta|<4.0$ with two end caps…
The Low-Gain Avalanche Diode (LGAD) is a new silicon detector and holds wide application prospects in particle physics experiments due to its excellent timing resolution. The LGAD with a pixel size of 1.3 mm $\times$ 1.3 mm was used to…
Low-Gain Avalanche Detectors (LGADs) are characterized by a fast rise time (500 ps) and extremely good time resolution (down to 17 ps). The intrinsic low granularity of LGADs and the large power consumption of readout chips for precise…
This work presents the first measurements performed on the Timespot1 ASIC. As the second prototype developed for the TimeSPOT project, the ASIC features a 32x32 channels hybrid-pixel matrix. Targeted to space-time tracking applications in…
We present the first characterization results of Timespot1, an ASIC designed in CMOS 28 nm technology, featuring a $32 \times 32$ pixel matrix with a pitch of $55 ~ \mu m$. Timespot1 is the first small-size prototype, conceived to readout…
We present the design and performance characterization results of the novel Fermilab Constant Fraction Discriminator ASIC (FCFD) developed to readout low gain avalanche detector (LGAD) signals by directly using a constant fraction…
A second monolithic silicon pixel prototype was produced for the MONOLITH project. The ASIC contains a matrix of hexagonal pixels with 100 {\mu}m pitch, readout by a low-noise and very fast SiGe HBT frontend electronics. Wafers with 50…
We present the optimization and performance characterization of the second-generation Fermilab Constant Fraction Discriminator ASIC (FCFD), designed for the readout of AC-coupled low-gain avalanche detector (LGAD) strip-sensors. The FCFD is…
The next-generation ALICE 3 experiment at the High-Luminosity LHC (HL-LHC) requires detector technologies that combine fine spatial resolution, fast timing, and an extremely low material budget. This paper presents the design,…
The present article introduces a novel ASIC architecture, designed in the context of the ATLAS Tile Calorimeter upgrade program for the High-Luminosity phase of the Large Hadron Collider at CERN. The architecture is based on…
We designed a versatile analog front-end chip, called LTARS, for TPC-applications, primarily targeted at dual-phase liquid Ar-TPCs for neutrino experiments and negative-ion $\mu$-TPCs for directional dark matter searches. Low-noise…