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Adiabatic Quantum-Flux-Parametron (AQFP) logic is a promising emerging device technology with six orders of magnitude lower power than CMOS. However, AQFP is challenged by the fact that every gate must be clocked, where proper data transfer…

Realization of logic circuits in graphene with an energy gap (EG) remains one of the main challenges for graphene electronics. We found that large transport EGs (>100 meV) can be fulfilled in dual-gated bilayer graphene underneath a simple…

Conventional circulators are made of magnetic ferrites and suffer from a cumbersome architecture, incompatibility with integrated circuit technology and inability for high frequency applications. To overcome these limitations, here we…

Approximate computing is a new computing paradigm. One important area of it is designing approximate circuits for FPGA. Modern FPGAs support dual-output LUT, which can significantly reduce the area of FPGA designs. Several existing works…

We have computationally demonstrated logic function implementations using lateral and vertical multi-contact phase change devices integrated with CMOS circuitry, which use thermal cross-talk as a coupling mechanism to implement logic…

The AIPC concept is gaining popularity, and more and more hybrid CPUs will be running AI models on client devices. However, the current AI inference framework overlooks the imbalanced hardware capability of hybrid CPUs, leading to low…

State-of-the-art in-memory computation has recently emerged as the most promising solution to overcome design challenges related to data movement inside current computing systems. One of the approaches to performing in-memory computation is…

Dual-material double-gate tunnel field effect transistor (DMDG TFET) is a promising candidate for low-power, high-speed electronics due to enhanced electrostatic control and superior switching characteristics. Integrating a pocket region…

Memtranstor that correlates charge and magnetic flux via nonlinear magnetoelectric effects has a great potential in developing next-generation nonvolatile devices. In addition to multi-level nonvolatile memory, we demonstrate here that…

Ternary logic is expected to increase the area efficiency of VLSI due to its expressiveness compared to the traditional binary logic. This paper proposes a new symmetric ternary logic and a systematic logic composition methodology that…

Field-effect transistors based on band-to-band tunneling (BTBT) have gained a lot of recent interest due to their potential for reducing power dissipation in integrated circuits. In this paper we present a detailed performance comparison…

Low-level sensory data processing in many Internet-of-Things (IoT) devices pursue energy efficiency by utilizing sleep modes or slowing the clocking to the minimum. To curb the share of stand-by power dissipation in those designs,…

The switching time of a magnet in a spin current based majority gate depends on the input vector combination, and this often restricts the speed of majority-based circuits. To address this issue, this work proposes a novel two-phase scheme…

Although the hardware complexity of the analog self-interference canceller in full duplex Multiple Input Multiple Output (MIMO) designs does not necessarily scale with the number of transceiver antennas, exploiting the benefits of analog…

Introducing spin-polarized carriers in semiconductor lasers reveals an alternative path to realize room-temperature spintronic applications, beyond the usual magnetoresistive effects. Through carrier recombination, the angular momentum of…

A new proposal is given for designing a non-volatile, completely spin logic device, that can be reprogrammed for different functional classical logical operations. We use the concept of bias driven spin dependent circular current and…

Some important VLSI adder circuits are implemented using quantum dots (qd) and Spin Polarized Scanning Tunneling Microscopy (SPSTM) in Single Spin Logic (SSL) paradigm. A simple comparison between these adder circuits shows that the mirror…

We extend the analogy between charge-based bipolar semiconductor electronics and spin-based unipolar electronics by considering unipolar spin transistors with different equilibrium spin splittings in the emitter, base, and collector. The…

Fast combinational multipliers with large bit widths can occupy significant silicon area, which also drives up power consumption. Area can be reduced through resource sharing (i.e., folding) at the expense of lower throughput, which is…

Throughout the world, the numbers of researchers or hardware designer struggle for the reducing of power dissipation in low power VLSI systems. This paper presented an idea of using the power gating structure for reducing the sub threshold…