Single Spin Logic Implementation of VLSI Adders
Quantum Physics
2011-11-23 v1
Abstract
Some important VLSI adder circuits are implemented using quantum dots (qd) and Spin Polarized Scanning Tunneling Microscopy (SPSTM) in Single Spin Logic (SSL) paradigm. A simple comparison between these adder circuits shows that the mirror adder implementation in SSL does not carry any advantage over CMOS adder in terms of complexity and number of qds, opposite to the trend observed in their charge-based counterparts. On the contrary, the transmission gate adder, Static and Dynamic Manchester carry gate adders in SSL reduce the complexity and number of qds, in harmony with the trend shown in transistor adders.
Cite
@article{arxiv.1111.5086,
title = {Single Spin Logic Implementation of VLSI Adders},
author = {Soumitra Shukla and Bahniman Ghosh},
journal= {arXiv preprint arXiv:1111.5086},
year = {2011}
}
Comments
9 pages, 18 figures