Related papers: Threshold Voltage variation with respect to Gate g…
A common issue in low temperature measurements of enhancement-mode metal-oxide-semiconductor (MOS) field-effect transistors (FETs) in the low electron density regime is the high contact resistance dominating the device impedance. In that…
In this paper, we have presented the impact of the gate leakage through thin gate dielectrics (SiO2 and high-\k{appa} gate dielectric) on the subthreshold characteristics of the tunnel field effect transistors (TFET) for a low operating…
In this work, the threshold voltage instability of normally-off p-GaN high electron mobility transistors (HEMTs) has been investigated by monitoring the gate current density during device on-state. The origin of the gate current variations…
Narrow-channel accumulated body nMOSFET devices with p-type side-gates surrounding the active area have been electrically characterized between 100 and 400 K with varied side-gate biasing (Vside). The subthreshold slope (SS) and drain…
Gate-All-Around Field-Effect Transistors (GAAFETs), now entering high-volume production as successors to fin field-effect transistor technology, are enabling continued scaling and enhanced performance in advanced semiconductor nodes.…
We have performed numerical modeling of dual-gate ballistic n-MOSFET's with channel length of the order of 10 nm, including the effects of quantum tunneling along the channel and through the gate oxide. Our analysis includes a…
A MOSFET threshold voltage extraction method covering the entire range of drain-to-source voltage, from linear to saturation modes, is presented. Transconductance-to-current ratio is obtained from MOSFET transfer characteristics measured at…
Tunnel field effect transistor (TFET) devices are attractive as they show good scalability and have very low leakage current. However they suffer from low on-current and high threshold voltage. In order to employ the TFET for circuit…
We study the channel width scaling of back-gated MoS2 metal-oxide-semiconductor field-effect transistors (MOSFETs) from 2 {\mu}m down to 60 nm. We reveal that the channel conductance scales linearly with channel width, indicating no evident…
We present a scaling theory of two-dimensional (2D) field effect transistors (FETs). For devices with channel thickness less than 4 nm, the device electrostatics is dominated by the physical gate oxide thickness and not the effective oxide…
The potential barrier between source and gate in HEMTs and between source and channel in MOSFET controls the current output and the velocity injection of electrons in the channel [1], [2]. In non self aligned structures the electric field…
Results of quantum mechanical simulations of the influence of edge disorder on transport in graphene nanoribbon metal oxide semiconductor field-effect transistors (MOSFETs) are reported. The addition of edge disorder significantly reduces…
Nanofabricated metal gate electrodes are commonly used to confine and control electrons in electrostatically defined quantum dots. However, these same gates impart strain-induced potential fluctuations that can potentially impair device…
Scaling transistors' dimensions has been the thrust for the semiconductor industry in the last 4 decades. However, scaling channel lengths beyond 10 nm has become exceptionally challenging due to the direct tunneling between source and…
In nanometer scaled CMOS devices significant increase in the subthreshold, the gate and the reverse biased junction band-to-band-tunneling (BTBT) leakage, results in the large increase of total leakage power in a logic circuit. Leakage…
The trench gate MOSFET has established itself as the most suitable power device for low to medium power applications by offering the lowest possible ON resistance among all MOS devices. The evolution of the trench gate power MOSFET has been…
In this work, quantum ballistic simulation study of a III-V tri-gate MOSFET has been presented. At the same time, effects of device parameter variation on ballistic, subthrshold and short channel performance is observed and presented. The…
Process-related and stress-induced changes in threshold voltage are major variability concerns in ultra-scaled CMOS transistors. The device designers consider this variability as an irreducible part of the design problem and use different…
We performed a comprehensive scaling study of Schottky barrier carbon nanotube transistors using self-consistent, atomistic scale simulations. We restrict our attention to Schottky barrier carbon nanotube FETs whose metal source/drain is…
This paper addresses the question of whether a ``rigid molecule'' (one which does not deform in an external field) used as the conducting channel in a standard three-terminal MOSFET configuration can offer any performance advantage relative…