Related papers: Cryogenic Memory Architecture Integrating Spin Hal…
Heavy computational demands from artificial intelligence (AI) leads the research community to explore the design space for functional materials that can be used for high performance memory and neuromorphic computing hardware. Novel device…
This paper describes a new memristor crossbar architecture that is proposed for use in a high density cache design. This design has less than 10% of the write energy consumption than a simple memristor crossbar. Also, it has up to 4 times…
We present experimental results and macrospin simulations of the switching characteristics of orthogonal spin-transfer devices incorporating an out-of-plane magnetized polarizing layer and an in-plane magnetized spin valve device at…
Cryogenic systems necessitate extensive data transmission between room-temperature and cryogenic environments, as well as within the cryogenic temperature domain. High-speed, low-power data transmission is pivotal to enabling the deployment…
The possible use of spin and magnets in place of charge and capacitors to store and process information is well known. Magnetic tunnel junctions are being widely investigated and developed for magnetic random access memories. These are two…
Deep Learning neural networks are pervasive, but traditional computer architectures are reaching the limits of being able to efficiently execute them for the large workloads of today. They are limited by the von Neumann bottleneck: the high…
Progress in high-performance computing demands significant advances in memory technology. Among novel memory technologies that promise efficient device operation on a sub-ns timescale, resistance switching between charge ordered phases of…
A new concept for nonvolatile superconducting memories is proposed. The devices combine ferromagnetic dots for the storage of the data and Josephson junctions for their readout. Good scalability is expected for large scale integration.…
High capacity and scalable memory systems play a vital role in enabling our desktops, smartphones, and pervasive technologies like Internet of Things (IoT). Unfortunately, memory systems are becoming increasingly prone to faults. This is…
In this work, we propose valley-coupled spin-hall memories (VSH-MRAMs) based on monolayer WSe2. The key features of the proposed memories are (a) the ability to switch magnets with perpendicular magnetic anisotropy (PMA) via VSH effect and…
Superconducting computing promises enhanced computational power in both classical and quantum approaches. Yet, scalable and fast superconducting memories are not implemented. Here, we propose a fully superconducting memory cell based on the…
Owing to the maturity of complementary metal oxide semiconductor (CMOS) microelectronics, qubits realized with spins in silicon quantum dots (QDs) are considered among the most promising technologies for building scalable quantum computers.…
As spin-orbit-torque magnetic random-access memory (SOT-MRAM) is gathering great interest as the next-generation low-power and high-speed on-chip cache memory applications, it is critical to analyze the magnetic tunnel junction (MTJ)…
Phase change memory (PCM) relies on a reversible transition between amorphous and crystalline states of a material, and stands as a promising candidate for next-generation, energy-efficient data storage and neuromorphic hardware. Here, we…
Biologically inspired recurrent neural networks, such as reservoir computers are of interest in designing spatio-temporal data processors from a hardware point of view due to the simple learning scheme and deep connections to Kalman…
Ultra-fast \& low-power superconductor single-flux-quantum (SFQ)-based CNN systolic accelerators are built to enhance the CNN inference throughput. However, shift-register (SHIFT)-based scratchpad memory (SPM) arrays prevent a SFQ CNN…
As nanoelectronics approaches the nanometer scale, a massive effort is underway to identify the next scalable logic technology beyond Complementary Metal Oxide Semiconductor (CMOS) computing. Such computing technology needs to improve…
Scaling fault tolerant quantum computers, especially cryogenic systems based on the surface code, to millions of qubits is challenging due to poorly-scaling data processing and power consumption overheads. One key hurdle is the design of…
The realization of chiral spin textures - comprising myriad distinct, nanoscale arrangements of spins with topological properties - has established pathways for engineering robust, energy-efficient and scalable elements for non-volatile…
Superconductor electronics (SCE) is a promising complementary and beyond CMOS technology. However, despite its practical benefits, the realization of SCE logic faces a significant challenge due to the absence of dense and scalable…