Related papers: Development of FEB Configuration Test Board for AT…

A completely New Small Wheel (NSW) will be constructed for ATLAS Phase-1 upgrade. Small-Strip Thin-Gap-Chamber (sTGC) will devote to the trigger function of NSW. A full-size sTGC quadruplet consists of 4 layers, and will need 4 pad…

The ATLAS experiment will replace the present Small Wheel (SW) detector with a New Small Wheel detector (NSW) aiming to improve the performance of muon triggering and precision tracking in the endcap region at the High-Luminosity LHC.…

The Pad Front End Board (pFEB) and the Strip Front End Board (sFEB) are developed for the ATLAS Phase-I sTGC Trigger Upgrade. The pFEB is used to to gather and analyze pads trigger, and the sFEB is developed to accept the pad trigger to…

The Address in Real Time Data Driver Card (ADDC) is designed to transmit the trigger data in the Micromegas detector of the ATLAS New Small Wheel (NSW) upgrade. The ART signals are generated by the front end ASIC, named VMM chip, to…

This paper presents an analysis of the updated version of the Front-End Board (FEB) for the NectarCAM camera, developed for the Cherenkov Telescope Array Observatory (CTAO). The FEB is a critical component responsible for reading and…

A new TDC chip has been developed for the COMPASS experiment at CERN. The resulting ASIC offers an unprecedented degree of flexibility and functionality. Its capability to handle highest hit and trigger input rates as well as its low power…

We describe a novel high-speed front-end electronic board (FEB) for interfacing an array of 32 Silicon Photo-multipliers (SiPM) with a computer. The FEB provides individually adjustable bias on the SiPMs, and performs low-noise analog…

T2K is a long baseline neutrino experiment, entering Phase II with a Near Detector upgrade. The T2K near detector (ND280) upgrade consists of the installation of three new detector systems: a plastic scintillator neutrino active target…

In the upgrade of ATLAS experiment, the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector…

Many accelerators require considerable electronic systems for tests, verification, and operation. In Shenzhen Superconducting Soft X-ray Free Electron Laser (S3FEL), to meet the early tests and verification of various systems, save…

High luminosity conditions at the LHC pose many unique challenges for potential silicon based track trigger systems. One of the major challenges is data formatting, where hits from thousands of silicon modules must first be shared and…

We will use EPICS toolkit [1] to build a prototype for upgrading BEPC control system. The purposes are for the following three aspects: (1) Setup a network based distributed control system with EPICS. (2) Study some front-end control…

High Voltage CMOS sensors are a promising technology for tracking detectors in collider experiments. Extensive R&D studies are being carried out by the ATLAS Collaboration for a possible use of HV-CMOS in the High Luminosity LHC upgrade of…

It is proposed to upgrade the endcap time-of-flight (ETOF) of the Beijing Spectrometer III (BESIII) with multi-gap resistive plate chamber (MRPC), aiming at overall time resolution about 80 ps. After the entire electronics system is ready,…

The STS-MUCH-XYTER (SMX) chip is a front-end ASIC dedicated to the readout of Silicon Tracking System (STS) and Muon Chamber (MUCH) detectors in the Compressed Baryonic Matter (CBM) experiment. The production of the ASIC and the front-end…

The ATLAS detector is set to undergo a substantial upgrade termed the "Phase-II" upgrade during the Long-Shutdown in preparation for the start of operation of the High Luminosity Large Hadron Collider (HL-LHC). This paper describes the…

Interest by the U.S. Navy in the development and deployment of advanced controls in future shipboard platforms has motivated the development of the Controls Evaluation Framework (CEF) for use in investigating dynamics present in complex…

An automatic clock synchronizing method implemented in field programmable gate array (FPGA) is proposed in this paper. It is developed for the clock system which will be applied in the end-cap time of flight (ETOF) upgrade of the Beijing…

This proceeding provides an expanded overview of the Fast Interaction Trigger (FIT) system performance, focusing on new developments such as the prospective integration of the ALICE Low-Level Front-End Device (ALFRED) into the Detector…

A front-end readout electronics system has been developed for silicon strip detectors. The system uses an application specific integrated circuit (ASIC) ATHED to realize multi-channel E&T measurement. The slow control of ASIC chips is…