Related papers: A Driver ASIC for Scientific CCD Detectors Using 1…

We present the optimization and performance characterization of the second-generation Fermilab Constant Fraction Discriminator ASIC (FCFD), designed for the readout of AC-coupled low-gain avalanche detector (LGAD) strip-sensors. The FCFD is…

.On the basis of requirement of CSNS, we designed a TDC chip with temperature compensation function in this paper, which employed TSMC 180nm process. Using delay unit bufx8 as the major method, delay lines in each level delayed input signal…

We present the second prototype of a time-to-digital (TDC) ASIC for the upgrade of the ATLAS Monitored Drift Tube (MDT) detector for High-Luminosity LHC operations. Compared to the first prototype, triple modular redundancy has been…

This paper presents a novel approach utilizing a scalable neural decoder application-specific integrated circuit (ASIC) based on metal oxide memristors in a 180nm CMOS technology. The ASIC architecture employs in-memory computing with…

This paper presents the design and characterisation of a front-end prototype ASIC for the ATLAS High Granularity Timing Detector, which is planned for the High-Luminosity phase of the LHC. This prototype, called ALTIROC1, consists of a…

A 12 bit Pipeline ADC fabricated in a 0.18 $\mu$m pure digital CMOS technology is presented. Its nominal conversion rate is 110MS/s and the nominal supply voltage is 1.8V. The effective number of bits is 10.4 when a 10MHz input signal with…

This paper presents a fully-integrated CMOS temperature sensor for densely-distributed thermal monitoring in systems on chip supporting dynamic voltage and frequency scaling. The sensor front-end exploits a sub-threshold PMOS-based circuit…

This paper describes the design and testing results of an 8 channels preamplifier-discriminator circuit based on a resistive feedback Transimpedance Amplifier architecture and a Leading-Edge Discriminator stage for fast high-accuracy time…

The ABCStar is a mixed-signal front-end readout ASIC for the strips sensor portion of the ATLAS ITk detector being developed as part of the High-Luminosity LHC upgrade. In pre-production testing, a subtle design flaw was uncovered in the…

The upgrade of ATLAS Liquid Argon Calorimeter (LAr) Phase-1 trigger requires high-speed, low-latency data transmission to read out the Lar Trigger Digitizer Board (LTDB). A dual-channel transmitter ASIC LOCx2 have been designed and…

ColdADC is a custom ASIC digitizer implemented in 65 nm CMOS technology using specialized techniques for long-term reliability in cryogenic environments. ColdADC was developed for use in the DUNE Far Detector complex, which will consist of…

We present the recent development of a lightweight detector capable of accurate spatial, timing, and amplitude resolution of charged particles. The technology is based on double-sided double-metal p+\,--\,n\,--\,n+ micro-strip silicon…

ALDO2 is a multi-function, adjustable, low dropout linear regulator designed in onsemi I3T80 0.35~$\mu$m HV CMOS technology for use in HEP detectors that adopt silicon photomultipliers (SiPMs). The chip features four independent regulators,…

A wide swing charge sensitive amplifier (CSA) has been developed, as a part of a front-end electronics (FEE) readout ASIC, for a prototype silicon tungsten (Si-W) based electromagnetic (EM) calorimeter. The CSA, designed in 0.35 $\mu$m…

We present a novel design and the test results of a 4-channel driver for an array of Vertical-Cavity Surface-Emitting Lasers (VCSELs). This ASIC, named cpVLAD and fabricated in a 65 nm CMOS technology, has on-chip charge pumps and is for…

A monolithic silicon pixel prototype produced for the MONOLITH ERC Advanced project was irradiated with 70 MeV protons up to a fluence of 1 x 10^16 1 MeV n_eq/cm^2. The ASIC contains a matrix of hexagonal pixels with 100 {\mu}m pitch,…

This contribution to LCWS2016 presents recent developments within the CLICdp collaboration. An updated scenario for the staged operation of CLIC has been published; the accelerator will operate at 380 GeV, 1.5 TeV and 3 TeV. The lowest…

CCD was born in Bell Laboratories in 1969 and has been widely used in various fields. Its ultra-low noise and high quantum efficiency make it work well in particle physics, high energy physics, nuclear physics and astrophysics. Nowadays,…

The design and evaluation on the NSLS-II beamline of the 3FI application specific integrated circuit (ASIC) bump-bonded to a simply, planar, two-dimensionally segmented silicon sensor is presented. The ASIC was developed for Full-Field…

This work presents the 8-channel FastIC+, a low-power consumption and highly configurable multi-channel front-end ASIC with internal digitization, for the readout of photo-sensors with picosecond time resolution and intrinsic gain. This…