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Time-to-Digital Converters (TDCs) are a crucial tool in a wide array of fields, in particular for quantum communication, where time taggers performance can severely affect the quality of the entire application. Nowadays, FPGA-based TDCs…

This paper analyzes faster-than-Nyquist (FTN) signaling within a consistent framework based on a fixed time-bandwidth product (TBP), resolving potential ambiguities present in finite blocklength analysis. A key feature of FTN is its ability…

Application Specific Integrated Circuits (ASICs) are used in space-borne instruments for signal processing and detector readout. The electrical interface of these ASICs to frontend printed circuit boards (PCBs) is commonly accomplished with…

The PICOSEC detector concept uses a micro-pattern gaseous detector (MPGD) amplification structure combined with a Cerenkov radiator coated with a semi-transparent photocathode to provide below tens of picosecond-level precision timing…

The aim of this work is to develop high precision Time-of-Flight (TOF) devices based on high refractive index solid Cherenkov radiators read out by silicon photomultipliers (SiPMs). Cherenkov light is prompt and therefore ideal for reaching…

The KM3NeT neutrino telescope will be composed of many optical modules, each of them containing 31 (3") photomultipliers, connected to a Central Logic Board. The Central Logic Board integrates Time to Digital Converters that measure Time…

We introduce a wireless RF network concept for capturing sparse event-driven data from large populations of spatially distributed autonomous microsensors, possibly numbered in the thousands. Each sensor is assumed to be a microchip capable…

Industrial control systems present numerous challenges from the communication systems perspective: clock synchronization, deterministic behavior, low latency, high reliability, flexibility, and scalability. These challenges are mostly…

In this paper we present a novel high-resolution multi-channel FPGA-based time-to-digital converter (TDC). We designed and implemented a complex electronic circuit on the FPGA, whose overall accuracy is several orders of magnitude greater…

Time-Aware Shaper (TAS) is a time-triggered scheduling mechanism that ensures bounded latency for time-critical Scheduled Traffic (ST) flows. The Linux kernel implementation (a.k.a TAPRIO) has limited capabilities due to varying CPU…

We have designed, implemented and tested a time-to-digital converter core in a low-cost Spartan-6 FPGA. Our design exploits the finite propagation speed in carry chains to realize a delay line in which the propagation distance of the…

Triplet-based Spike Timing Dependent Plasticity (TSTDP) is a powerful synaptic plasticity rule that acts beyond conventional pair-based STDP (PSTDP). Here, the TSTDP is capable of reproducing the outcomes from a variety of biological…

Clock synchronization procedures are mandatory in most physical experiments where event fragments are readout by spatially dislocated sensors and must be glued together to reconstruct key parameters (e.g. energy, interaction vertex etc.) of…

Silicon carbide detectors exhibit good detection performance such as fast time resolution, high radiation tolerances, high breakdown voltage and low temperature sensitivity and have been studied for detection applications. Meanwhile,…

Spiking Neural Networks (SNNs) offer high energy efficiency and event-driven computation, ideal for low-power edge AI. Their hardware implementation on FPGAs, however, faces challenges due to heavy computation, large memory use, and limited…

We present a multifunctional, antenna-integrated capacitive sensing (MAiCaS) platform for passive, wireless, and real-time cardiovascular monitoring. Unlike conventional systems that require separate sensors and wireless modules, our device…

Intelligent reflecting surface (IRS) has drawn a lot of attention recently as a promising new solution to achieve high spectral and energy efficiency for future wireless networks. By utilizing massive low-cost passive reflecting elements,…

This work presents the 8-channel FastIC+, a low-power consumption and highly configurable multi-channel front-end ASIC with internal digitization, for the readout of photo-sensors with picosecond time resolution and intrinsic gain. This…

The SAMpler for PICosecond time (SAMPIC) chip has been designed by a collaboration including CEA/IRFU/SEDI, Saclay and CNRS/LAL/SERDI, Orsay. It benefits from both the quick response of a time to digital converter and the versatility of a…

Robust, reliable, and deterministic networks are essential for a variety of applications. In order to provide guaranteed communication network services, Time-Sensitive Networking (TSN) unites a set of standards for time-synchronization,…