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Random number generation is a key technology that is useful in a variety of ways. Random numbers are often used to generate keys for data encryption. Random numbers generated at a sufficiently long length can encrypt sensitive data and make…

Hardware Architecture · Computer Science 2022-09-12 Jacob Hammond

In engineering applications sorting is an important and widely studied problem where execution speed and resources used for computation are of extreme importance, especially if we think about real time data processing. Most of the…

Hardware Architecture · Computer Science 2012-06-08 Rourab Paul , Suman Sau , Amlan Chakrabarti

Ultrafast ultrasound imaging is essential for advanced ultrasound imaging techniques such as ultrasound localization microscopy (ULM) and functional ultrasound (fUS). Current ultrafast ultrasound imaging is challenged by the ultrahigh data…

High-throughput imaging workflows, such as Parallel Rapid Imaging with Spectroscopic Mapping (PRISM), generate data at rates that exceed conventional real-time processing capabilities. We present a scalable FPGA-based preprocessing pipeline…

Hardware Architecture · Computer Science 2025-11-26 Weichien Liao

With the development of hardware-optimized deployment of spiking neural networks (SNNs), SNN processors based on field-programmable gate arrays (FPGAs) have become a research hotspot due to their efficiency and flexibility. However,…

Neural and Evolutionary Computing · Computer Science 2026-01-06 Hou Yue , Xiang Shuiying , Zou Tao , Huang Zhiquan , Shi Shangxuan , Guo Xingxing , Zhang Yahui , Zheng Ling , Hao Yue

Applications of Trigger Units (TU) can be found in almost all accelerators at CERN. The requirements in terms of operating frequencies, configuration or modes of operation change from one application to another, how-ever, in terms of design…

Accelerator Physics · Physics 2018-03-28 D. Barrientos , J. Molendijk , G. Hagmann

As IoT and edge inference proliferate,there is a growing need to simultaneously optimize area and delay in lookup-table (LUT)-based multipliers that implement large numbers of low-bitwidth operations in parallel. This paper proposes a…

Hardware Architecture · Computer Science 2025-10-27 Misaki Kida , Shimpei Sato

Training of convolutional neural networks (CNNs)on embedded platforms to support on-device learning is earning vital importance in recent days. Designing flexible training hard-ware is much more challenging than inference hardware, due to…

Machine Learning · Computer Science 2019-08-20 Shreyas Kolala Venkataramanaiah , Yufei Ma , Shihui Yin , Eriko Nurvithadhi , Aravind Dasu , Yu Cao , Jae-sun Seo

This work demonstrates the first non-reciprocal network based on switched low-loss acoustic delay lines. The 4-port circulator is built upon a recently reported frequency-independent, programmable, non-reciprocal framework based on switched…

Signal Processing · Electrical Eng. & Systems 2019-09-17 Ruochen Lu , Tomas Manzaneque , Yansong Yang , Liuqing Gao , Anming Gao , Songbin Gong

Nowadays a diverse range of physiological data can be captured continuously for various applications in particular wellbeing and healthcare. Such data require efficient methods for classification and analysis. Deep learning algorithms have…

Machine Learning · Computer Science 2018-11-02 Hamid Soleimani , Aliasghar , Makhlooghpour , Wilten Nicola , Claudia Clopath , Emmanuel. M. Drakakis

In this work, we introduce a new hardware architecture for decoding correlated errors in quantum LDPC codes. The decoder is based on message passing and exploits the structure of the detector error model obtained through the recently…

With present-day detectors in high energy physics one often faces fast analog pulses of a few nanoseconds length which cover large dynamic ranges. In many experiments both amplitude and timing information have to be measured with high…

Embedded field programmable gate array (eFPGA) technology allows the implementation of reconfigurable logic within the design of an application-specific integrated circuit (ASIC). This approach offers the low power and efficiency of an ASIC…

Hardware Architecture · Computer Science 2024-08-29 Julia Gonski , Aseem Gupta , Haoyi Jia , Hyunjoon Kim , Lorenzo Rota , Larry Ruckman , Angelo Dragone , Ryan Herbst

This project develops a pseudo-random number generator (PRNG) using the logistic map, implemented in Verilog HDL on an FPGA and processes its output through a Central Limit Theorem (CLT) function to achieve a Gaussian distribution. The…

Reconfigurable architectures like Field Programmable Gate Arrays (FPGAs) have been used for accelerating computations in several domains because of their unique combination of flexibility, performance, and power efficiency. However, FPGAs…

Hardware Architecture · Computer Science 2023-04-26 Murat Isik , Kayode Inadagbo , Hakan Aktas

This paper proposes and evaluates a novel architecture for a low-power Time-to-Digital Converter with high resolution, optimized for both integration in multichannel chips and high rate operation (40 Mconversion/s/channel). This converter…

Signal Processing · Electrical Eng. & Systems 2023-06-02 Florent Bouyjou

This study presents an efficient field-programmable gate array (FPGA) implementation of a polynomial spline function-based statistical compression algorithm designed to address the critical challenge of massive data transfer bandwidth in…

Image and Video Processing · Electrical Eng. & Systems 2026-02-12 Zhenya Zang , Mike Davies , Istvan Gyongy

In this study, a novel type of Fourier transform radio spectrometer (termed as all-digital radio spectrometer; ADRS) has been developed in which all functionalities comprising a radio spectrometer including a sampler and Fourier computing…

Instrumentation and Methods for Astrophysics · Physics 2021-05-12 Atsushi Nishimura , Takeru Matsumoto , Teppei Yonetsu , Yuka Nakao , Shinji Fujita , Hiroyuki Maezawa , Toshikazu Onishi , Hideo Ogawa

In this paper, we propose a 'full-stack' solution to designing high capacity and low latency on-chip cache hierarchies by starting at the circuit level of the hardware design stack. First, we propose a novel Gain Cell (GC) design using…

Hardware Architecture · Computer Science 2021-10-07 Sarabjeet Singh , Neelam Surana , Pranjali Jain , Joycee Mekie , Manu Awasthi

In-time particle trajectory reconstruction in the Large Hadron Collider is challenging due to the high collision rate and numerous particle hits. Using GNN (Graph Neural Network) on FPGA has enabled superior accuracy with flexible…

Hardware Architecture · Computer Science 2023-06-28 Shi-Yu Huang , Yun-Chen Yang , Yu-Ru Su , Bo-Cheng Lai , Javier Duarte , Scott Hauck , Shih-Chieh Hsu , Jin-Xuan Hu , Mark S. Neubauer