Related papers: Neutron induced strike: On the likelihood of multi…
Experimental means to characterize delay faults induced by bit flips and SEUs in I/O blocks of SRAM-based FPGAs are proposed. A delay fault up to 6.2ns sensitized by an events chain is reported.
Logic Encryption is one of the most popular hardware security techniques which can prevent IP piracy and illegal IC overproduction. It introduces obfuscation by inserting some extra hardware into a design to hide its functionality from…
With the large-scale integration and use of neural network models, especially in critical embedded systems, their security assessment to guarantee their reliability is becoming an urgent need. More particularly, models deployed in embedded…
In this paper we present the impact of classical electronics constraints on a solid-state quantum dot logical qubit architecture. Constraints due to routing density, bandwidth allocation, signal timing, and thermally aware placement of…
Over past years, the easy accessibility to the large scale datasets has significantly shifted the paradigm for developing highly accurate prediction models that are driven from Neural Network (NN). These models can be potentially impacted…
Noisy quantum computers suffer from readout or measurement error. It is a classical bit-flip error due to which state "1" is read out as "0" and vice-versa. The probability of readout error shows a state dependence i.e., flipping…
Programming errors, defective hardware components (such as hard disk spindle defects), and environmental hazards can lead to invalid memory operations. In addition, less predictable forms of environmental stress, such as radiation, thermal…
The increasing density of modern DRAM has heightened its vulnerability to Rowhammer attacks, which induce bit flips by repeatedly accessing specific memory rows. This paper presents an analysis of bit flip patterns generated by advanced…
In digital circuits, a Flip-Flop (FF) is a circuit element that has two stable states which can be used to store and remember state information. The state of the circuit can be changed by applying signals to the control input. FFs are the…
Sub-bit model compression seeks storage below one bit per weight; as magnitudes are aggressively compressed, the sign bit becomes a fixed-cost bottleneck. Across Transformers, CNNs, and MLPs, learned sign matrices resist low-rank…
In this paper, we investigate the impact of bit flip errors in FPGA memories in control electronics on quantum computing systems. FPGA memories are integral in storing the amplitude and phase information pulse envelopes, which are essential…
Fault injection attacks (FIA) pose significant security threats to embedded systems as they exploit weaknesses across multiple layers, including system software, instruction set architecture (ISA), microarchitecture, and physical hardware.…
FinFETs have replaced the conventional bulk CMOS transistors in the sub-20nm technology. One of the key issues to consider is, the vulnerability of FinFET based circuits to multiple node charge collection due to neutron-induced strikes. In…
Quantum information transport over micron to millimeter scale distances is critical for the operation of practical quantum processors based on spin qubits. One method of achieving a long-range interaction is by coherent electron spin…
A simple physical model for calculation of the ion-induced soft error rate in space environment has been proposed, based on the phenomenological cross section notion. Proposed numerical procedure is adapted to the multiple cell upset…
In modern transistor based logic gates, the impact of noise on computation has become increasingly relevant since the voltage scaling strategy, aimed at decreasing the dissipated power, has increased the probability of error due to the…
Modern processors utilize an increasingly large register set to facilitate efficient floating point and SIMD computation. This large register set is a burden for operating systems, as its content needs to be saved and restored when the…
Spin qubits in Silicon quantum dots can have long coherence times, yet their manipulation relies on the exchange interaction, through which charge noise can induce decoherence. Charge traps near the interface of a Si heterostructure lead to…
In this paper, using 3D Technology Computer-Aided-Design (TCAD) simulations, we show that it is possible to design a static random-access memory (SRAM) using gate-all-around field-effect-transistor (GAA-FET) technology so that it is immune…
Silicon offers an attractive material platform for hardware realization of quantum computing. In this study, a microscopic stochastic simulation method is developed to model the effect of random interface charge traps in silicon…