Related papers: Hardware Architecture of Complex K-best MIMO Decod…

Overcoming the conventional trade-off between throughput and bit error rate (BER) performance, versus computational complexity is a long-term challenge for uplink Multiple-Input Multiple-Output (MIMO) detection in base station design for…

The paper describes the design and hardware implementation of 32-bit encrypted MIPS processor based on MIPS pipeline architecture. The organization of pipeline stages in such a way that pipeline can be clocked at high frequency. Encryption…

MIMO systems are considered as most promising for wireless communications. However, with an increasing number of radio front ends the corresponding energy consumption and costs become an issue, which can be relieved by the utilization of…

Accurate noise estimation is essential for fault-tolerant quantum computing, as decoding performance depends critically on the fidelity of the circuit-level noise parameters. In this work, we introduce a differentiable Maximum Likelihood…

FPGA technology can offer significantly hi\-gher performance at much lower power consumption than is available from CPUs and GPUs in many computational problems. Unfortunately, programming for FPGA (using ha\-rdware description languages,…

Massive spatial modulation (SM)-MIMO, which employs massive low-cost antennas but few power-hungry transmit radio frequency (RF) chains at the transmitter, is recently proposed to provide both high spectrum efficiency and energy efficiency…

This paper proposes an low power approximate multiplier architecture for deep neural network (DNN) applications. A 4:2 compressor, introducing only a single combination error, is designed and integrated into an 8x8 unsigned multiplier. This…

In this paper, we present a low-complexity algorithm for detection in high-rate, non-orthogonal space-time block coded (STBC) large-MIMO systems that achieve high spectral efficiencies of the order of tens of bps/Hz. We also present a…

Programmable Logic Devices (PLDs) continue to grow in size and currently contain several millions of gates. At the same time, research effort is going into higher-level hardware synthesis methodologies for reconfigurable computing that can…

In this work, we present a simplification and a corresponding hardware architecture for hard-decision recursive projection-aggregation (RPA) decoding of Reed-Muller (RM) codes. In particular, we transform the recursive structure of RPA…

In this paper, we propose a systematic low density generator matrix (LDGM) code ensemble, which is defined by the Bernoulli process. We prove that, under maximum likelihood (ML) decoding, the proposed ensemble can achieve the capacity of…

In this paper, the problem of designing a linear precoder for Multiple-Input Multiple-Output (MIMO) systems in conjunction with Quadrature Amplitude Modulation (QAM) is addressed. First, a novel and efficient methodology to evaluate the…

Multimodal Large Language Models (MLLMs) are undergoing rapid progress and represent the frontier of AI development. However, their training and inference efficiency have emerged as a core bottleneck in making MLLMs more accessible and…

The use of low-resolution digital-to-analog converters (DACs) for transmit precoding provides crucial energy efficiency advantage for massive multiple-input multiple-output (MIMO) implementation. This paper formulates a quadrature amplitude…

Multiple Input Multiple Output (MIMO) wireless communication link has been theoretically proven to be reliable and capable of achieving high capacity. However, these two advantageous characteristics tend to be addressed separately in many…

Index modulation (IM) reduces the power consumption and hardware cost of the multiple-input multiple-output (MIMO) system by activating part of the antennas for data transmission. However, IM significantly increases the complexity of the…

To leverage high-frequency bands in 6G wireless systems and beyond, employing massive multiple-input multipleoutput (MIMO) arrays at the transmitter and/or receiver side is crucial. To mitigate the power consumption and hardware complexity…

Binary quantization represents the most extreme form of compression, reducing weights to +/-1 for maximal memory and computational efficiency. While recent sparsity-aware binarization achieves sub-1-bit compression via weight pruning, it…

Lattice reduction is a popular preprocessing strategy in multiple-input multiple-output (MIMO) detection. In a quest for developing a low-complexity reduction algorithm for large-scale problems, this paper investigates a new framework…

Modern chip design is complex, and there is a crucial need for early-stage prediction of key design-quality metrics like timing and routing congestion directly from Verilog code (a commonly used programming language for hardware design). It…